OFFSET CALIBRATION SCHEMES IN TIME-BASED 3D NAND-BASED VECTOR-MATRIX MULTIPLIER CIRCUIT
For a vector-matrix multiplication of a neural network with analog value weights stored differentially on pairs of memory cells, each memory cell of the pair is sensed by one of a pair of sensing circuits. To provide accurate values, the pair of sensing circuits need to be matched, but, due to processing variations, there will be some offset between the two. Methods are presented for compensating for the offset between the pair of sensing circuits of a neuron circuit. In one approach, when the difference between the result of the differential sensing is a count, a digital correction can be made by subtracting an offset count to compensate for device mismatch. In another approach, an offset current is provided to one the sensing circuits to compensate for device mismatch. An additional approach uses dedicated columns of the NAND array to provide offset compensation.
1 . A non-volatile memory device, comprising:
a control circuit configured to connect to an array of non-volatile memory cells storing weight values of a neural network, each of the weight values stored differentially in a pair of the memory cells concurrently connectable to a corresponding one of a pair of bit lines, the control circuit comprising:
a first sensing circuit comprising a first capacitor and connectable to a first bit line of a bit line pair configured to connect to a corresponding first memory cell of a pair of the memory cells differentially storing a first weight value;
a second sensing circuit comprising a second capacitor and connectable to a second bit line of the bit line pair configured to connect to a corresponding second memory cell of the pair of the memory cells differentially storing the first weight value; and
offset correction circuitry connectable to one or both of the first sensing circuit and the second sensing circuit and configured to compensate for processing variations between the first sensing circuit and the second sensing circuit,
the control circuit configured to perform a vector-matrix multiplication between an input vector and the weight values of the neural network where, to perform the vector-matrix multiplication of the input vector and the first weight value, the control circuit is configured to:
selectively connect the first memory cell to the first bit line based on a value of the input vector;
selectively connect the second memory cell to the second bit line based on the value of the input vector;
connect the first capacitor to discharge through the first bit line as selectively connected to the first memory cell based on the value of the input vector;
connect the second capacitor to discharge through the second bit line as selectively connected to the second memory cell based on the value of the input vector;
determine a difference in voltage levels between the first capacitor as discharged through the first bit line as selectively connected to the first memory cell based on the value of the input vector;
convert the difference in voltage levels to a count;
compensate the count by the offset correction circuitry to compensate for the processing variations; and
determine a product of the input vector and the first weight value from the compensated count.
2 . The non-volatile memory device of claim 1 , wherein the control circuit is formed on a control die, the non-volatile memory device further comprising:
a memory die including the array, the memory die separate from and bonded to the control die.
3 . The non-volatile memory device of claim 1 , wherein, to compensate the count by the offset correction circuitry to compensate for the processing variations, the control circuit is further configured to:
subtract an offset count value from the count.
4 . The non-volatile memory device of claim 3 , wherein the control circuit is further configured to:
determine the offset count value in a calibration process as part of a power on sequence.
5 . The non-volatile memory device of claim 1 , wherein, to compensate the count by the offset correction circuitry to compensate for the processing variations, the control circuit is further configured to compensate the difference in voltage levels.
6 . The non-volatile memory device of claim 5 , wherein, to compensate the count by the offset correction circuitry to compensate for the processing variations, the control circuit is further configured to:
supply an offset current to one of the first bit line or the second bit line when respectively discharging first capacitor through the first bit line or discharging second capacitor through the second bit line.
7 . The non-volatile memory device of claim 6 , wherein the control circuit is further configured to:
determine the offset current in a calibration process as part of a power on sequence.
8 . The non-volatile memory device of claim 5 , wherein the offset correction circuitry includes one or more additional memory cells connectable to the first bit line or the second bit line and, to compensate the count by the offset correction circuitry to compensate for the processing variations, the control circuit is further configured to:
concurrently with one or both of connecting the first capacitor to discharge through the first bit line and connecting the second capacitor to discharge through the second bit line, additionally discharging one or both of the first capacitor and the second capacitor to discharge through the one or more additional memory cells.
9 . The non-volatile memory device of claim 8 , wherein the control circuit is further configured to:
program the additional memory cells in a calibration process.
10 . The non-volatile memory device of claim 1 , wherein the weight values of the neural network are analog values.
11 . The non-volatile memory device of claim 10 , wherein the analog weight values are stored as current levels.
12 . The non-volatile memory device of claim 1 , wherein the input vector is multi-bit valued.
13 . The non-volatile memory device of claim 1 , further comprising:
the array of non-volatile memory cells, wherein the array has a three dimensional NAND architecture, the first memory cell belonging to a first NAND string of the array and the second memory cell belonging to a second NAND string of the array.
14 . A method, comprising:
receiving an input vector value for a neural network;
performing a multiplication between the input vector value and a weight of the neural network, the weight stored differentially in a pair of memory cells including a first memory cell of a first NAND string having a select gate connecting the first NAND string to a first bit line and a second memory cell of a second NAND string having a select gate connecting the second NAND string to a second bit line, including:
connecting a first sensing circuit having a first capacitor to discharge the first capacitor for a first interval through the first bit line as selectively connected to the first memory cell based on the value of the input vector while receiving a reference current on the first bit line;
connecting a second sensing circuit having a second capacitor to discharge the second capacitor for the first interval through the second bit line as selectively connected to the second memory cell based on the value of the input vector while receiving the reference current on the second bit line;
subsequent to discharging the first capacitor and the second capacitor for the first interval, comparing a charge level on the first capacitor to a charge level on the second capacitor; and
determining a product of the multiplication between the input vector value and the weight of the neural network from the comparison of the charge level on the first capacitor to the charge level on the second capacitor and from an offset value between the first sensing circuit and the second sensing circuit; and
prior to performing the multiplication between the input vector value and the weight of the neural network, calibrating the offset value.
15 . The method of claim 14 , further comprising:
calibrating the offset value as part of a power on sequence.
16 . The method of claim 14 , wherein determining the product of the multiplication between the input vector value and the weight of the neural network includes:
converting the comparison of the charge level on the first capacitor to the charge level on the second capacitor to a first count value; and
subtracting a calibrated offset count from the first count value.
17 . The method of claim 14 , further comprising:
generating the offset value by providing an offset current to either the first bit line or the second bit line while respectively discharging either the first capacitor or the second capacitor.
18 . The method of claim 14 , further comprising:
generating the offset value by, concurrently with discharging the first capacitor through the first bit line and discharging the second capacitor through the second bit line, discharging one or both of the first capacitor and second capacitor through one or more additional memory cells.
19 . A non-volatile memory device, comprising:
an array of non-volatile memory cells having a NAND architecture in which each NAND string includes a select gate through which the NAND string is connected to a corresponding bit line, the memory cells storing weight values of a neural network, each weight value stored as a differential a pair of memory cells on different NAND strings;
a sensing circuit, comprising:
a first sensing circuit including a first capacitor connectable to a first bit line of a bit line pair configured to connect to a corresponding first memory cell of a pair of the memory cells differentially storing a first weight value;
a second sensing circuit including a second capacitor connectable to a second bit line of a bit line pair configured to connect to a corresponding second memory cell of the pair of the memory cells differentially storing the first weight value; and
an offset correction circuit configured to compensate for processing variations between the first sensing circuit and the second sensing circuit, and
one or more control circuits configured to connect to the array and to the sensing circuit and configured to perform a vector-matrix multiplication between an input vector and the weight values of the neural network where, to perform the vector-matrix multiplication of the input vector and the first weight value, the one or more control circuits are configured to:
connect the first capacitor to discharge for a first interval through the first bit line as selectively connected to the first memory cell based on the value of the input vector;
connect the second capacitor to discharge for the first interval through the second bit line as selectively connected to the second memory cell based on the value of the input vector;
subsequent to discharging the first capacitor and the second capacitor for the first interval, compare a charge level on the first capacitor to a charge level on the second capacitor; and
determine a value of the vector-matrix multiplication from the comparison of the charge level on the first capacitor to the charge level on the second capacitor as compensated by the offset correction circuit.
20 . The non-volatile memory device of claim 19 , wherein the one or more control circuits are further configured to:
prior to determining the value of the vector-matrix multiplication, calibrating the offset correction circuit in response to a power on command.