NON-VOLATILE MEMORY WITH VARIABLE ON PITCH
A memory device is provided with a memory block that includes a stacked structure of alternating ones of a plurality of word lines and a plurality of insulating layers. The plurality of word lines include a plurality of memory cells. A plurality of memory holes extend through the word lines and through the insulating layers. The memory holes having variable diameters such that the diameter of one of the memory holes at one of the word lines differs from the diameter of the same memory hole at another of the word lines. The insulating layers have varying thicknesses which are determined as a function of the diameters of the memory holes in areas of the respective insulating layers.
1 . A memory device, comprising:
a memory block including a stacked structure of alternating ones of a plurality of word lines and a plurality of insulating layers, the plurality of word lines including a plurality of memory cells;
a plurality of memory holes extending through the word lines and through the insulating layers, the memory holes having variable diameters such that the diameter of one of the memory holes at one of the word lines differs from the diameter of the same memory hole at another of the word lines; and
the insulating layers having varying thicknesses, the thicknesses of the insulating layers being determined as a function of the diameters of the memory holes in areas of the respective insulating layers.
2 . The memory device as set forth in claim 1 , wherein in a first location of the memory block, the memory holes have a relatively larger first diameter and in a second location of the memory block, the memory holes have a relatedly smaller second diameter, and
wherein a first insulating layer in the first location of the memory block has a relatively lesser first thickness and wherein a second insulating layer in the second location of the memory block has a relatively greater second thickness.
3 . The memory device as set forth in claim 1 , wherein the insulating layers are dielectric layers.
4 . The memory device as set forth in claim 1 , wherein at least some of the insulating layers in the memory block have a thickness (T Oxide ) that is calculated according to the formula
T
Oxide
=
(
X
p
Y
p
2
-
π
CD
2
8
)
Constant
,
where Xp is a pitch between rows of memory holes in a first horizontal direction; Yp is a pitch between rows of memory holes in a second horizontal direction that is orthogonal to the first horizontal direction; CD is a diameter of the memory holes at the given location; and Constant is the same for the at least some insulating layers.
5 . The memory device as set forth in claim 1 , wherein the at least some insulating layers includes all of the insulating layers of the memory block.
6 . The memory device as set forth in claim 1 , wherein the memory holes have frustoconical shapes.
7 . The memory device as set forth in claim 6 , wherein the memory holes have upper portions and lower portions, and wherein each of the upper and lower portions has a frustoconical shape.
8 . A method of making a memory device, comprising the steps of:
building a memory block of alternating ones of a plurality of word lines and a plurality of insulating layers;
forming a plurality of memory holes through the plurality of word lines and insulating layers, the memory holes having variable diameters such that the diameter of one of the memory holes at one of the word lines differs from the diameter of the same memory hole at another of the word lines; and
wherein the insulating layers are formed with varying thicknesses, the thicknesses of the insulating layers being determined as a function of the diameters of the memory holes in areas of the respective insulating layers.
9 . The method as set forth in claim 8 , wherein in a first location of the memory block, the memory holes have a relatively larger first diameter and in a second location of the memory block, the memory holes have a relatedly smaller second diameter, and
wherein a first insulating layer in the first location of the memory block has a relatively lesser first thickness and wherein a second insulating layer in the second location of the memory block has a relatively greater second thickness.
10 . The method as set forth in claim 8 , wherein the insulating layers are dielectric layers.
11 . The method as set forth in claim 8 , wherein at least some of the insulating layers in the memory block have a thickness (T Oxide ) that is calculated according to the formula
T
Oxide
=
(
X
p
Y
p
2
-
π
CD
2
8
)
Constant
,
where Xp is a pitch between rows of memory holes in a first horizontal direction; Yp is a pitch between rows of memory holes in a second horizontal direction that is orthogonal to the first horizontal direction; CD is a diameter of the memory holes at the given location; and Constant is the same for the at least some insulating layers.
12 . The method as set forth in claim 8 , wherein the at least some insulating layers includes all of the insulating layers of the memory block.
13 . The method as set forth in claim 8 , wherein the memory holes have frustoconical shapes.
14 . The method as set forth in claim 13 , wherein the memory holes have upper portions and lower portions, and wherein each of the upper and lower portions has a frustoconical shape.
15 . A computing system, comprising:
a processor unit;
a plurality of non-volatile memory units in electrical communication with the processor units;
at least one of the non-volatile memory units including;
a memory block including a stacked structure of alternating ones of a plurality of word lines and a plurality of insulating layers, the plurality of word lines including a plurality of memory cells;
a plurality of memory holes extending through the word lines and through the insulating layers, the memory holes having variable diameters such that the diameter of one of the memory holes at one of the word lines differs from the diameter of the same memory hole at another of the word lines; and
the insulating layers having varying thicknesses, the thicknesses of the insulating layers being determined as a function of the diameters of the memory holes in areas of the respective insulating layers.
16 . The computing system as set forth in claim 15 , wherein in a first location of the memory block, the memory holes have a relatively larger first diameter and in a second location of the memory block, the memory holes have a relatedly smaller second diameter, and
wherein a first insulating layer in the first location of the memory block has a relatively lesser first thickness and wherein a second insulating layer in the second location of the memory block has a relatively greater second thickness.
17 . The computing system as set forth in claim 15 , wherein the insulating layers are dielectric layers.
18 . The computing system as set forth in claim 15 , wherein at least some of the insulating layers in the memory block have a thickness (T Oxide ) that is calculated according to the formula
T
Oxide
=
(
X
p
Y
p
2
-
π
CD
2
8
)
Constant
,
where Xp is a pitch between rows of memory holes in a first horizontal direction; Yp is a pitch between rows of memory holes in a second horizontal direction that is orthogonal to the first horizontal direction; CD is a diameter of the memory holes at the given location; and Constant is the same for the at least some insulating layers.
19 . The computing system as set forth in claim 15 , wherein the at least some insulating layers includes all of the insulating layers of the memory block.
20 . The computing system as set forth in claim 15 , wherein the memory holes have frustoconical shapes.