IP Library Patent Application 18775668
Patent Application
App. No. 18/775,668

POWER REALLOCATION FOR MEMORY DEVICE

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Quick Facts
Patent No.
US None
App. No.
18/775,668
Filed
Jul 17, 2024
Art Unit
OPAP
USPC
703/13
Abstract

A data storage device including, in one implementation, a number of memory die packages disposed on a substrate within the data storage device. Each memory die package has a die density that includes one or more memory dies. The die density of each memory die package is configured to provide an even thermal distribution across the number of memory die packages. The respective die densities of two memory of the die packages are different from each other.

Claims (48)

1 . A method comprising:

performing, with an electronic processor, a thermal analysis of a memory device having an initial memory device design, the memory device including a plurality of memory die packages, each memory die package having a memory die density;

performing a thermal leveling operation on the memory device;

updating the thermal analysis based on the thermal leveling operation;

determining whether the updated thermal analysis meets a predetermined threshold; and

generating a final memory device design in response to determining that the updated thermal analysis meets the predetermined threshold.

2 . The method of claim 1 , further comprising performing a second thermal leveling operation of the memory device in response to determining that the updated thermal analysis does not meet the predetermined threshold.

3 . The method of claim 1 , wherein the performing the thermal leveling operation includes reallocating power to one or more of the plurality of memory die packages.

4 . The method of claim 3 , wherein the reallocating power to the one or more memory die packages in the memory device includes varying respective memory die densities of the plurality of memory die packages.

5 . The method of claim 4 , wherein the respective memory die densities are one or more selected from a group comprising:

a two-die density,

a four-die density,

an eight-die density, and

a sixteen-die density.

6 . The method of claim 1 , wherein the predetermined threshold comprises one or more of:

a thermal threshold,

a performance threshold, and

a power consumption threshold.

7 . The method of claim 6 , wherein the thermal threshold comprises maintaining a junction temperature of each of the plurality of memory die packages below a predetermined value.

8 . The method of claim 6 , wherein the thermal threshold comprises maintaining an average junction temperature for all of the plurality of memory die packages below a predetermined value.

9 . The method of claim 1 , wherein performing, with the electronic processor, the thermal analysis of the memory device having the initial memory device design further includes

receiving thermal information from one or more thermal sensors attached to the memory device, and

generating a thermal image from the thermal information, the thermal image including higher temperature image portions illustrated with darker shading and lower temperature image portions illustrated with lighter shading.

10 . The method of claim 9 , wherein the one or more thermal sensors includes one or more infrared imagers, multiple thermocouples, or a combination thereof.

11 . The method of claim 1 , wherein the predetermined threshold is an average junction temperature of the plurality of memory die packages below 55° C.

12 . The method of claim 1 , wherein the thermal analysis is a simulated thermal analysis.

13 . A non-transitory computer-readable medium having stored thereon software instructions that, when executed by an electronic processor, causes the electronic processor to perform a set of operations comprising:

performing a thermal analysis of a memory device including a plurality of memory die packages, each memory die package having a memory die density;

performing a thermal leveling operation of the memory device;

updating the thermal analysis based on the thermal leveling operation;

determining whether the updated thermal analysis meets a predetermined threshold; and

generating an updated memory device design in response to determining that the updated thermal analysis meets the predetermined threshold.

14 . The non-transitory computer-readable medium of claim 13 , wherein performing the thermal levelling operation includes reallocating power to the one or more memory die packages in the memory device.

15 . The non-transitory computer-readable medium of claim 14 , wherein the reallocating power to the one or more memory die packages in the memory device includes varying respective memory die densities of the plurality of memory die packages.

16 . The non-transitory computer-readable medium of claim 15 , wherein the respective memory die densities are one or more selected from a group comprising one or more of:

a two-die density,

a four-die density,

an eight-die density, and

a sixteen-die density.

17 . The non-transitory computer-readable medium of claim 13 , wherein the predetermined threshold comprises one or more of:

a thermal threshold,

a performance threshold, and

a power consumption threshold.

18 . The non-transitory computer-readable medium of claim 13 , wherein performing the thermal analysis of the memory device having the initial memory device design further includes

receiving thermal information from one or more thermal sensors attached to the memory device, and

generating a thermal image from the thermal information, the thermal image including higher temperature image portions illustrated with darker shading and lower temperature image portions illustrated with lighter shading.

19 . The non-transitory computer-readable medium of claim 18 , wherein the one or more thermal sensors includes one or more infrared imagers, multiple thermocouples, or a combination thereof.

20 . The non-transitory computer-readable medium of claim 13 , wherein the predetermined threshold is an average junction temperature of the plurality of memory die packages below 55° C.

Assignments (6)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0486 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069169/0572 →
PATENT COLLATERAL AGREEMENT (AR) Recorded Aug 23, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0695 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2024
From: BHAGATH, SHRIKAR; JENKINS, DEAN; ZHANG, HEDAN; WINKLER, BRET; YE, NING
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 068012/0287 →