MULTI-PLANE LEAKAGE DETECTION IN NONVOLATILE MEMORY

1 . An apparatus comprising:

one or more control circuits configured to connect to a plurality of planes of a nonvolatile memory array, the one or more control circuits are configured to:

apply leak-detection voltages to a plurality of selected blocks, each selected block located in a respective plane of the plurality of planes, obtain a leak-detection indicator for each selected block in parallel and compare each leak-detection indicator with a reference in series.

2 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to apply leak-detection conditions including word line voltages to each selected block in parallel.

3 . The apparatus of claim 2 , wherein the one or more control circuits are further configured to obtain the leak-detection indicator as a respective leak-detection voltage for each selected block and to output the respective leak-detection voltages in parallel.

4 . The apparatus of claim 3 , wherein the one or more control circuits include a multiplexer connected to receive the respective leak-detection voltages for the plurality of selected blocks in parallel and output a selected leak-detection voltage of the respective leak-detection voltages.

5 . The apparatus of claim 4 , wherein the one or more control circuits further include an Analog-to-Digital Converter (ADC) connected to the multiplexer to receive the selected leak-detection voltage from the multiplexer and generate a multi-bit code from the selected leak-detection voltage.

6 . The apparatus of claim 5 , wherein the one or more control circuits are configured to perform a binary search to obtain a digital code that corresponds to the multi-bit code.

7 . The apparatus of claim 1 , wherein the one or more control circuits include, for each plane of the plurality of planes, a current mirror with a first branch connected to a respective selected block and current control circuit and a second branch connected to an output node that provides the leak-detection indicator.

8 . The apparatus of claim 1 , wherein the plurality of planes comprises four planes, the one or more control circuits include a leak-detection indicator circuit for each plane, the leak-detection indicator circuits are connected to a multiplexer and analysis circuit to enable analysis of each leak-detection indicator in series.

9 . The apparatus of claim 1 , wherein the one or more control circuits are located on a control die that is configured to be bonded to a memory die that includes the nonvolatile memory array.

10 . The apparatus of claim 1 , wherein the nonvolatile memory array is a NAND memory.

11 . A method comprising:

applying word line leak-detection conditions to a first selected block in a first plane to obtain a first word line leak-detection indicator;

while applying the word line leak-detection conditions to the first selected block, applying word line leak-detection conditions to a second selected block in a second plane to obtain a second word line leak-detection indicator;

comparing the first word line leak-detection indicator with one or more reference; and

subsequently comparing the second word line leak-detection indicator with the one or more reference.

12 . The method of claim 11 , further comprising:

while applying the word line leak-detection conditions to the first selected block, applying the word line leak-detection conditions to a third selected block in a third plane to obtain a third word line leak-detection indicator; and

while applying the word line leak-detection conditions to the first selected block, applying word line leak-detection conditions to a fourth selected block in a fourth plane to obtain a fourth word line leak-detection indicator.

13 . The method of claim 12 , further comprising:

subsequent to comparing the second word line leak-detection indicator with the one or more reference, comparing the third word line leak-detection indicator with the one or more reference; and

subsequent to comparing the third word line leak-detection indicator with the one or more reference, comparing the fourth word line leak-detection indicator with the one or more reference.

14 . The method of claim 11 , wherein comparing the first word line leak-detection indicator with one or more reference includes comparing the first word line leak-detection indicator with a series of references selected from a range of references according to a binary search.

15 . The method of claim 14 , further comprising:

converting the first word line leak-detection indicator to a first digital code; and

converting the second word line leak-detection indicator to a second digital code.

16 . The method of claim 15 , wherein converting the first and second word line leak-detection indicators to the first and second digital codes includes performing a binary search.

17 . The method of claim 16 , wherein comparing the first and second word line leak-detection indicators with the one or more reference includes comparing the first and second digital codes with a digital reference.

18 . A data storage system comprising:

a plurality of nonvolatile memory cells arranged in a plurality of planes; and

means for applying leak-detection voltages to selected blocks, each selected block located in a respective plane of the plurality of planes to obtain a leak-detection indicator for each selected block in parallel and comparing each leak-detection indicator with one or more reference in series.

19 . The data storage system of claim 18 , wherein the plurality of nonvolatile memory cells are formed on a memory die and the means for applying and comparing is located on a control die that is bonded to the memory die to form an integrated memory assembly.

20 . The data storage system of claim 18 , wherein the plurality of nonvolatile memory cells are arranged in NAND strings that are connected to word lines and the leak-detection voltages are applied to word lines to detect word line leakage.