NONVOLATILE MEMORY WITH VOLTAGE OVERSHOOT MITIGATION

1 . An apparatus comprising:

one or more control circuits configured to connect to a plurality of nonvolatile memory cells, wherein the one or more control circuits are configured to:

apply a predetermined voltage on one or more word lines connected to the nonvolatile memory cells in a memory access operation and limit overshoot of the predetermined voltage by controlling a discharge pathway at an output terminal according to an analog control signal, the analog control signal is proportional to voltage overshoot of the predetermined voltage.

2 . The apparatus of claim 1 , wherein the discharge pathway is directly connected to the output terminal and controlling the discharge pathway includes controlling a discharge current between the output terminal and a ground terminal.

3 . The apparatus of claim 2 , wherein the discharge pathway is formed by a PMOS device that has a first terminal directly connected to the output terminal, a second terminal directly connected to the ground terminal and a gate that receives the analog control signal.

4 . The apparatus of claim 3 , further comprising an NMOS device that has a first terminal connected to a supply voltage and a second terminal connected to the first terminal of the PMOS device and to the output terminal to form a push-pull output stage.

5 . The apparatus of claim 1 , wherein the analog control signal is generated by a bias circuit that includes a first NMOS device, a second NMOS device and a current source connected in series between a supply voltage and ground with an output for the analog control signal located between the second NMOS device and the current source.

6 . The apparatus of claim 5 , wherein a gate terminal of the first NMOS device receives a gate signal that is proportional to the overshoot of the predetermined voltage.

7 . The apparatus of claim 6 , wherein the gate signal is generated by a first NMOS device controlled by an output of an amplifier, the amplifier includes a first input terminal connected to receive an indicator signal that indicates voltage at the output terminal, a second input terminal connected to the predetermined voltage, and an output terminal connected to the gate terminal of the first NMOS device.

8 . The apparatus of claim 7 , wherein the first NMOS device, a resistor and a second NMOS device are connected in series between ground and a supply voltage.

9 . The apparatus of claim 1 , wherein the plurality of nonvolatile memory cells are arranged in a 3D NAND structure.

10 . The apparatus of claim 1 , wherein the one or more control circuits are formed on a control die, the plurality of nonvolatile memory cells are formed on a memory die and the control die and memory die are bonded to form an integrated memory assembly.

11 . A method comprising:

generating a memory access voltage at an output terminal that is connected to one or more word lines of a NAND memory structure;

providing an analog feedback signal from the output terminal;

generating a gate voltage according to a difference between the analog feedback signal and a reference voltage;

from the gate voltage, generating an analog control signal that is a function of the difference between the analog feedback signal and the reference voltage; and

discharging the output terminal through a discharge pathway, a discharge current through the discharge pathway controlled by the analog control signal such that discharge current increases according to the difference between the analog feedback signal and the reference voltage.

12 . The method of claim 11 , wherein the discharge pathway is formed by a PMOS device and discharging the output terminal includes applying the analog control signal to a gate terminal of the PMOS device to cause a discharge current that increases in proportion to the difference between the analog feedback signal and the reference voltage.

13 . The method of claim 12 , wherein providing the analog feedback signal from the output terminal includes providing the analog feedback signal from a node of a voltage divider that is connected between the output terminal and ground.

14 . The method of claim 11 , wherein generating the gate voltage includes providing the analog feedback signal and the reference voltage to input terminals of an amplifier such that an output of the amplifier increases according to the difference between the analog feedback signal and the reference voltage.

15 . The method of claim 14 , wherein generating the gate voltage further includes providing the output of the amplifier to a control gate of a first NMOS device that is connected in series with a resistor and a second NMOS device between ground and a supply voltage, the gate voltage generated between the first NMOS device and the resistor.

16 . The method of claim 11 , wherein generating the memory access voltage at the output terminal includes providing the gate voltage to an NMOS device that is connected between a supply voltage and the output terminal, the discharge pathway is formed by a PMOS device and the NMOS device and PMOS device form a push-pull output stage.

17 . The method of claim 11 , wherein the one or more word lines are unselected word lines in a read or write operation, the memory access voltage is a pass voltage and discharging the output terminal mitigates pass voltage overshoot on the unselected word lines.

18 . A storage system comprising:

a plurality of nonvolatile memory cells connected by word lines; and

means for applying a pass voltage on one or more unselected word lines in a read or write operation directed to the plurality of nonvolatile memory cells and limiting overshoot of the pass voltage by controlling a discharge current from an output terminal according to an analog control signal where the discharge current is proportional to the overshoot of the pass voltage.

19 . The storage system of claim 18 , wherein the plurality of nonvolatile memory cells are arranged in a 3D NAND structure.

20 . The storage system of claim 19 , wherein the 3D NAND structure is located on a memory die, the means for applying a pass voltage is located on a control die and the control die is bonded to the memory die to form an integrated memory assembly.