NON-VOLATILE MEMORY WITH LOCATION DEPENDENT CONTROL GATE VOLTAGE
A non-volatile memory is divided into multiple zones of non-volatile memory cells. During a sensing operation that includes concurrently sensing total output current from a bit line while the bit line is concurrently receiving output current from multiple non-volatile memory cells that are in different zones, different voltages are applied to selected word lines in different zones based on how far a respective zone is from the bit line driver.
1 . A non-volatile storage apparatus, comprising:
a bit line;
a plurality of non-volatile memory cells connected to the bit line; and
a control circuit connected to the plurality of non-volatile memory cells and the bit line, the control circuit is configured to:
concurrently apply different control gate voltages to different non-volatile memory cells of the plurality non-volatile memory cells, and
sense total output current from the bit line while the bit line is receiving output current from multiple non-volatile memory cells of the plurality of non-volatile memory cells in response to the different control gate voltages.
2 . The non-volatile storage apparatus of claim 1 , further comprising:
a bit line driver, the control circuit is configured to concurrently apply different control gate voltages to different non-volatile memory cells of the plurality non-volatile memory cells based on distance of a respective non-volatile memory cell from the bit line driver.
3 . The non-volatile storage apparatus of claim 1 , wherein:
the plurality of non-volatile memory cells are divided into multiple zones;
the control circuit is configured to concurrently apply different control gate voltages to different non-volatile memory cells by concurrently applying different control gate voltages to different zones of the multiple zones; and
the control circuit is configured to sense total output current from the bit line by sensing total output current from the bit line while the bit line is receiving output current from non-volatile memory cells in different zones in response to the different control gate voltages.
4 . The non-volatile storage apparatus of claim 1 , wherein:
the plurality of non-volatile memory cells are organized into blocks, each zone includes multiple blocks; and
the control circuit is configured to sense total output current from the bit line by sensing total output current from the bit line while the bit line is receiving output current from non-volatile memory cells in multiple blocks of multiple zones in response to the different control gate voltages.
5 . The non-volatile storage apparatus of claim 1 , further comprising:
a bit line driver, the plurality of non-volatile memory cells are divided into multiple zones, the control circuit is configured to concurrently apply different control gate voltages to different non-volatile memory cells by concurrently applying different control gate voltages to different zones of the multiple zones based on distance of a respective zone from the bit line driver, the control circuit is configured to sense total output current from the bit line by sensing total output current from the bit line while the bit line is receiving output current from non-volatile memory cells in different zones in response to the different control gate voltages.
6 . The non-volatile storage apparatus of claim 5 , wherein the control circuit is configured to concurrently apply different control gate voltages to different zones of the multiple zones by:
applying a base control gate voltage to a first zone closest to the bit line driver;
applying the base control gate voltage plus a first offset to a second zone farther from the bit line driver than the first zone; and
applying the base control gate voltage plus a second offset to a third zone farther from the bit line driver than the second zone.
7 . The non-volatile storage apparatus of claim 5 , wherein the control circuit is configured to concurrently apply different control gate voltages to different zones of the multiple zones by:
applying a base control gate voltage to a first zone closest to the bit line driver; and
applying the base control gate voltage plus customized offsets to other zones farther from the bit line driver than the first zone, the customized offsets are based on distance of a respective zone from the bit line driver.
8 . The non-volatile storage apparatus of claim 5 , wherein:
the plurality of non-volatile memory cells are organized into blocks, each zone includes multiple blocks; and
the control circuit is configured to sense total output current from the bit line by sensing total output current from the bit line while the bit line is receiving output current from non-volatile memory cells in multiple blocks of multiple zones in response to the different control gate voltages.
9 . The non-volatile storage apparatus of claim 1 , further comprising:
multiple word lines connected to control gates of the plurality of non-volatile memory cells and the control circuit, the control circuit is configured to concurrently apply different control gate voltages to different non-volatile memory cells of the plurality non-volatile memory cells via the word lines.
10 . The non-volatile storage apparatus of claim 9 , wherein:
the plurality of non-volatile memory cells are divided into multiple zones;
the control circuit is configured to concurrently apply different control gate voltages to different non-volatile memory cells by concurrently applying different control gate voltages to word lines in different zones such that word lines in each zone receive different control gate voltages than word lines in other zones; and
the control circuit is configured to sense total output current from the bit line by sensing total output current from the bit line while the bit line is receiving output current from non-volatile memory cells in different zones in response to the different control gate voltages.
11 . The non-volatile storage apparatus of claim 1 , further comprising:
a voltage source; and
a plurality of resistors connected to the voltage source for receiving a first voltage from the voltage source, each resistor of the plurality of resistors is connected to a different subset of the non-volatile memory cells for providing a different percentage of the first voltage to the respective subset of the non-volatile memory cells as the different control gate voltages.
12 . The non-volatile storage apparatus of claim 1 , further comprising:
multiple word lines connected to control gates of the plurality of non-volatile memory cells and the control circuit, the plurality of non-volatile memory cells are divided into multiple zones, the control circuit is configured to concurrently apply different control gate voltages to different non-volatile memory cells by concurrently applying different control gate voltages to word lines in different zones such that word lines in each zone receive different control gate voltages than word lines in other zones;
a voltage source; and
a plurality of resistors connected to the voltage source for receiving a first voltage from the voltage source, each resistor of the plurality of resistors is connected to a different zone such that each resistor is connected to control gates of non-volatile memory cells in its respective zone for providing a different percentage of the first voltage to non-volatile memory cells of its respective zone as the different control gate voltages.
13 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to concurrently apply different control gate voltages and sense total output current as part of an in-memory vector-matrix multiplication process.
14 . The non-volatile storage apparatus of claim 1 , further comprising:
select gates connected to the non-volatile memory cells; and
select lines connected to the select gates and the control circuit, the control circuit is configured to perform a vector-matrix multiplication process including: (i) the applying the different control gate voltages, (ii) applying an input vector to the select lines and (iii) the sensing the total output current.
15 . The non-volatile storage apparatus of claim 1 , further comprising:
select lines connected to the control circuit, the non-volatile memory cells are positioned on NAND strings, the NAND strings include select gates connected to the select lines, each of the NAND strings is connected to the bit line, the plurality of non-volatile memory cells are configured to store weight information, the plurality of non-volatile memory cells are divided into multiple zones, each zone includes one or more of the NAND strings such that different NAND strings are in different zones, the control circuit is configured to perform vector-matrix multiplication using the weight information stored in the non-volatile memory cells by: (i) applying an input vector to the select lines and (ii) sensing output current from the bit line while the bit line is concurrently receiving current from multiple NAND strings in multiple zones.
16 . A method of operating a non-volatile memory comprising a plurality of non-volatile memory cells connected to a bit line and multiple word lines, the plurality of non-volatile memory cells and the multiple word lines are divided into multiple zones, the method comprising:
concurrently applying different selected word line voltages to different zones of the multiple zones; and
sensing total output current from the bit line while the bit line is concurrently receiving output current from multiple non-volatile memory cells that are in different zones and are connected to different selected word lines that are receiving the different selected word line voltages.
17 . The method of claim 16 , wherein:
the concurrently applying different selected word line voltages to different zones of the multiple zones includes concurrently applying different selected word line voltages to different zones of the multiple zones based on distance of a respective zone from a common bit line driver, the common bit line driver is connected to the bit line.
18 . The method of claim 17 , wherein:
the plurality of non-volatile memory cells are organized into blocks, each zone includes multiple blocks; and
the sensing total output current from the bit line includes sensing total output current from the bit line while the bit line is receiving output current from non-volatile memory cells in multiple blocks of multiple zones in response to the different selected word line voltages.
19 . The method of claim 18 , further comprising:
storing weight information in the plurality of non-volatile memory cells by programming the plurality of non-volatile memory cells into a set of data states defined by current distributions, the non-volatile memory cells are positioned in NAND strings, the NAND strings include select gates connected to the select lines, each of the NAND strings is connected to the bit line, each zone includes one or more of the NAND strings such that different NAND strings are in different zones, the sensing total output current includes sensing total output current from the bit line while the bit line is concurrently receiving current from multiple NAND strings in multiple zones; and
performing vector-matrix multiplication using the weight information stored in the plurality of non-volatile memory cells by: (i) applying an input vector to select lines, (ii) the concurrently applying different selected word line voltages to different zones of the multiple zones and (iii) the sensing.
20 . A non-volatile storage apparatus, comprising:
a bit line driver;
a bit line connected to the bit line driver;
a non-volatile memory comprising a plurality of non-volatile memory cells connected to the bit line, the plurality of non-volatile memory cells are positioned in multiple blocks, the multiple blocks are grouped into zones, each zone includes multiple blocks; and
means for performing vector matrix multiplication in the non-volatile memory by concurrently sensing total output current from the bit line while the bit line is concurrently receiving output current from multiple non-volatile memory cells of the plurality of non-volatile memory cells that are in different zones in response to different control gate voltages applied to the memory cells that are in different zones based on how far a respective zone is from the bit line driver.