IP Library Patent Application 18825864
Patent Application
App. No. 18/825,864

SEMICONDUCTOR DEVICE WITH STRUCTURALLY REINFORCED CORNERS

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Quick Facts
Patent No.
US None
App. No.
18/825,864
Abstract

A semiconductor device is mounted to a printed circuit board by one or more capacitor. The capacitors provide a dual function of electrically and mechanically supporting the semiconductor device. Multiple semiconductor devices are formed on a panel of substrates. Support vias are formed in the saw street between adjacent substrate instances, at the corners of each substrate instance. Portions of these support vias remain at the corners of each semiconductor device when the devices are singulated from the panel. These portions of the support vias are used to bond the semiconductor devices to the capacitors on the printed circuit board.

Claims (36)

1 . A semiconductor device, comprising:

a substrate;

a semiconductor die mounted on a first side of the substrate;

electrical interconnections electrically coupling the semiconductor die to the substrate; and

at least a portion of a support via, formed at one or more corners of the substrate, the support via specifically made to mate with a capacitor to mount the semiconductor device on a printed circuit board (PCB).

2 . The semiconductor device of claim 1 , wherein the at least a portion of the support via comprises a portion of a support via, a remaining portion of the support via removed upon singulation of the semiconductor device from a panel.

3 . The semiconductor device of claim 1 , wherein the at least a portion of the support via formed at one or more corners comprises the at least a portion of a support via formed at each of four corners of the semiconductor device.

4 . The semiconductor device of claim 1 , wherein the at least a portion of the support via extends from a first major surface of the substrate to a second major surface of the substrate opposed to the first major surface.

5 . The semiconductor device of claim 1 , wherein the at least a portion of the support via extends from a first major surface of the substrate but not to a second major surface of the substrate opposed to the first major surface.

6 . The semiconductor device of claim 1 , further comprising a plurality of solder balls on first major surface of the substrate opposite a second major surface of the substrate including the semiconductor die, the solder balls configured to electrically and mechanically couple the semiconductor device to the PCB.

7 . The semiconductor device of claim 1 , wherein the semiconductor die is a flash memory die.

8 . The semiconductor device of claim 1 , wherein the semiconductor die is a controller die.

9 . A semiconductor assembly, comprising:

a printed circuit board (PCB);

a semiconductor device, comprising:

a substrate,

a semiconductor die mounted on a first side of the substrate, and

electrical interconnections electrically coupling the semiconductor die to the substrate; and

one or more capacitor structures, the one or more capacitor structures directly coupled to the semiconductor device to structurally support the semiconductor device on the substrate.

10 . The semiconductor assembly of claim 9 , wherein the capacitor structures comprise one or more of a capacitor having a pair of solder end posts, a solder end post by itself, and a dummy capacitor.

11 . The semiconductor assembly of claim 9 , wherein the capacitor structures comprise one or more capacitors, the one or more capacitors further providing electrical support to the semiconductor device.

12 . The semiconductor assembly of claim 9 , wherein the capacitor structures are positioned at one or more corners of the semiconductor device.

13 . The semiconductor assembly of claim 12 , wherein the capacitor structures are positioned at each of the corners of the semiconductor device.

14 . The semiconductor assembly of claim 9 wherein the capacitor structures are positioned along one or more sides of the semiconductor device, between corners of the semiconductor device.

15 . The semiconductor assembly of claim 9 , further comprising a portion of a support vias formed in the substrate, a capacitor structure of the one or more capacitor structures coupling to the portion of the support via.

16 . The semiconductor assembly of claim 15 , wherein the capacitor structure comprises a solder post, the solder post supporting a bottom surface of the portion of the support via and a side surface of the portion of the support via.

17 . The semiconductor assembly of claim 9 , further comprising a plurality of solder balls on first major surface of the substrate opposite a second major surface of the substrate including the semiconductor die, the solder balls configured to electrically and mechanically couple the semiconductor device to the PCB.

18 . The semiconductor assembly of claim 9 , wherein the one or more capacitor structures comprise two or more capacitors, and wherein two of the two or more capacitors are oriented along different axes.

19 . The semiconductor assembly of claim 9 , wherein the one or more capacitor structures comprise two or more capacitors, and wherein two of the two or more capacitors are positioned adjacent to each other at a single corner.

20 . A semiconductor assembly, comprising:

a printed circuit board (PCB);

a semiconductor device, comprising:

a substrate,

a semiconductor die mounted on a first side of the substrate, and

electrical interconnections electrically coupling the semiconductor die to the substrate; and

means for mechanically and electrically supporting the semiconductor device on the PCB.

Assignments (4)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0486 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2024
From: LIU, YANGMING
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 068501/0615 →