MULTILAYER ELECTRODE DEVICES AND METHOD OF MAKING THE SAME
A semiconductor structure includes a first field effect transistor including first source and drain regions located in a first portion of a semiconductor substrate, a first gate dielectric including a first metal oxide gate dielectric that includes a first portion of a dielectric metal oxide material, and a first gate electrode comprising a first metallic gate electrode that includes a first portion of a gate metallic material; and a second field effect transistor including second source and drain regions located in a second portion of the semiconductor substrate, a second gate dielectric including a silicon oxide gate dielectric, and a second gate electrode including a vertical stack of a doped semiconductor gate electrode and a second metallic gate electrode that includes a second portion of the gate metallic material.
1 . A semiconductor structure, comprising:
a first field effect transistor comprising first source and drain regions located in a first portion of a semiconductor substrate, a first gate dielectric comprising a first metal oxide gate dielectric, and a first gate electrode comprising a first metallic gate electrode that comprises a first portion of a gate metallic material; and
a second field effect transistor comprising second source and drain regions located in a second portion of the semiconductor substrate, a second gate dielectric comprising a silicon oxide gate dielectric, and a second gate electrode comprising a vertical stack of a doped semiconductor gate electrode and a second metallic gate electrode that comprises a second portion of the gate metallic material.
2 . The semiconductor structure of claim 1 , wherein the first gate electrode consists essentially of the first metallic gate electrode and excludes a doped semiconductor gate electrode.
3 . The semiconductor structure of claim 2 , wherein:
the second gate dielectric consists essentially of the silicon oxide gate dielectric, and excludes a metal oxide gate dielectric; and
the first gate dielectric comprises a stack of the first metal oxide gate dielectric and a first silicon oxide gate dielectric.
4 . The semiconductor structure of claim 1 , wherein:
the first field effect transistor comprises a lower voltage transistor than the second field effect transistor; and
the first gate dielectric is thinner than the second gate dielectric.
5 . The semiconductor structure of claim 1 , wherein:
a horizontal plane including topmost surfaces of the first source and drain regions is located above a horizontal plane including topmost surfaces of the second source and drain regions;
a horizontal plane including bottommost surfaces of the first source and drain regions is located above a horizontal plane including bottommost surfaces of the second source and drain regions; and
a bottom surface of the first metallic gate electrode is located above a horizontal plane including a bottom surface of the second metallic gate electrode.
6 . The semiconductor structure of claim 1 , wherein a bottom surface of the first gate dielectric is located above a horizontal plane including a top surface of the second gate dielectric.
7 . The semiconductor structure of claim 1 , wherein a bottom surface of a second metallic gate electrode is located below a horizontal plane including a bottom surface of the first metallic gate electrode.
8 . The semiconductor structure of claim 7 , wherein the silicon oxide gate dielectric contacts a bottom surface of the doped semiconductor gate electrode.
9 . The semiconductor structure of claim 7 , wherein the silicon oxide gate dielectric comprises:
a first portion having a first thickness and having a same area as the doped semiconductor gate electrode; and
a second portion having a second thickness that is less than the first thickness and not having any areal overlap within the doped semiconductor gate electrode.
10 . The semiconductor structure of claim 1 , wherein the doped semiconductor gate electrode contacts a bottom surface of the second metallic gate electrode and overlies the second gate dielectric.
11 . The semiconductor structure of claim 10 , wherein:
an interface between the doped semiconductor gate electrode and the second metallic gate electrode is located below a horizontal plane including a bottom surface of the first metallic gate electrode; and
sidewalls of the doped semiconductor gate electrode are vertically coincident with sidewalls of the second metallic gate electrode.
12 . The semiconductor structure of claim 1 , wherein top surfaces of the first gate electrode and the second gate electrode are located in a same horizontal plane.
13 . The semiconductor structure of claim 1 , wherein:
the first field effect transistor comprises a first inner dielectric gate spacer that laterally surrounds the first gate electrode and the first gate dielectric; and
the second field effect transistor comprises a second inner dielectric gate spacer that laterally surrounds the second gate electrode and an upper portion of the second gate dielectric and overlies a horizontally-extending portion of the first gate dielectric.
14 . The semiconductor structure of claim 13 , wherein:
the first field effect transistor comprises an outer dielectric gate spacer that laterally surrounds the first inner dielectric gate spacer and has a straight outer sidewall that vertically extends from a horizontal plane including a top surface of the first gate electrode to a top surface of a respective one of the first source and drain regions; and
the second field effect transistor comprises an outer dielectric gate spacer layer that comprises a vertically-extending portion that laterally surrounds the second inner dielectric gate spacer and a horizontally-extending portion overlies the horizontally-extending portion of the first gate dielectric and laterally protrudes outward from the vertically-extending portion of the second outer dielectric gate spacer.
15 . A method of forming a semiconductor structure, comprising:
locally recessing a segment of a top surface of a semiconductor substrate, wherein an unrecessed portion of the semiconductor substrate comprises a first horizontal top surface and a recessed portion of the semiconductor substrate comprises a second horizontal top surface that is vertically recessed relative to the first horizontal top surface;
forming an intermediate gate material assembly comprising a silicon oxide gate dielectric and a semiconductor gate electrode material portion over the second horizontal top surface;
forming a layer stack comprising at least one sacrificial gate electrode material layer over the intermediate gate material assembly and the first horizontal top surface;
patterning the layer stack and the intermediate gate material assembly, wherein a first in-process gate stack including a first patterned portion of the at least one sacrificial gate electrode material layer is formed over the first horizontal top surface and a second in-process gate stack including a second patterned portion of the at least one sacrificial gate electrode material layer is formed over the second horizontal top surface; and
replacing the first patterned portion and the second patterned portion of the at least one sacrificial gate electrode material layer with a first metallic gate electrode and a second metallic gate electrode, respectively.
16 . The method of claim 15 , further comprising:
depositing a gate semiconductor material layer over the first horizontal top surface and the second horizontal top surface; and
removing a portion of the gate semiconductor material layer from above the first horizontal top surface by performing a planarization process, wherein a remaining portion of the gate semiconductor material layer comprises the semiconductor gate electrode material portion.
17 . The method of claim 15 , further comprising:
forming a patterned hard mask layer over the intermediate gate material assembly and the first horizontal top surface;
forming shallow isolation trenches by etching portions of the intermediate gate material assembly and the semiconductor substrate that are not covered with the patterned hard mask layer; and
forming shallow trench isolation structures in the shallow isolation trenches, wherein the layer stack is formed over the shallow trench isolation structures.
18 . The method of claim 17 , further comprising:
forming a metallic barrier liner layer over the first horizontal top surface without covering the intermediate gate material assembly, wherein the layer stack is formed over the metallic barrier liner layer;
forming a patterned etch mask layer over the layer stack; and
anisotropically etching an unmasked portion of the at least one sacrificial gate electrode material layer selectively to the metallic barrier liner.
19 . The method of claim 18 , wherein:
the intermediate gate material assembly further comprises an etch-stop layer; and
unmasked portions of the etch-stop layer and the semiconductor gate electrode material portion are etched.
20 . The method of claim 15 , further comprising:
forming a planarization dielectric layer around the first in-process gate stack and the second in-process gate stack; and
forming a first gate cavity and a second gate cavity by removing the first patterned portion and the second patterned portion of the at least one sacrificial gate electrode material layer without removing a remaining portion of the semiconductor gate electrode material portion in the second in-process gate stack, wherein the second metallic gate electrode is formed directly on a top surface of the remaining portion of the semiconductor gate electrode material portion.