IP Library Granted Patent US 12,646,582
Granted Patent B2
US 12,646,582 · App. 18/903,283 · Granted Jun 2, 2026

Data storage device and method for dynamic bit-error-rate estimation scan (BES)

Inventors: Mahim Gupta (San Jose, CA); Jia Li (San Francisco, CA); Sugandha Sharma (Pleasanton, CA)
Assignee: Sandisk Technologies, Inc.
G11C29/44G11C16/349G11C16/26G11C29/50004
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Quick Facts
Patent No.
US 12,646,582
App. No.
18/903,283
Granted
Jun 2, 2026
Kind
B2
Abstract

A sensed read threshold voltage can sometimes vary from a write threshold voltage due to one or more factors, such as data retention issues and program disturb conditions. A bit-error-rate estimation scan (BES) can be used to calibrate and optimize read thresholds in this situation. However, as more wordlines are introduced, BES may not provide suitable calibration. In such situations, the BES can be re-performed on certain pages using an additional offset.

Claims (36)

1 . A data storage device comprising:

a memory; and

one or more processors, individually or in combination, configured to:

perform a first bit-error-rate estimation scan (BES) on a scan range in the memory, wherein the BES is performed using a first offset;

determine whether a page in the scan range comprises DAC shifts below a criterion; and

in response to determining that the page in the scan range comprises DAC shifts below the criterion, perform a second BES on the page, wherein the second BES is performed using a second offset.

2 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to determine whether the page in the scan range comprises DAC shifts below the criterion by monitoring syndrome weight versus BES shifts.

3 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to determine whether the page in the scan range comprises DAC shifts below the criterion by determining whether the DAC shifts are becoming increasingly negative and out of a range.

4 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to determine whether the page in the scan range comprises DAC shifts below the criterion by determining whether the page comprises an offset based on data-storage-device-level statistics.

5 . The data storage device of claim 1 , wherein the BES comprises BES5, which performs five memory senses.

6 . The data storage device of claim 5 , wherein performing the second BES using the second offset avoids performing BES7, which performs seven memory senses.

7 . The data storage device of claim 1 , wherein the page in the scan range comprises DAC shifts below the criterion in response to a first data retention condition.

8 . The data storage device of claim 1 , wherein the memory comprises multi-level memory cells.

9 . The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.

10 . The data storage device of claim 1 , wherein the memory comprises a two-dimensional memory.

11 . A storage system comprising:

a memory; and

means for:

performing a first bit-error-rate estimation scan (BES) on a scan range in the memory, wherein the BES is performed using a first offset;

identifying a page in the scan range that comprises DAC shifts below a criterion; and

performing a second BES on the page, wherein the second BES is performed using a second offset.

12 . In a data storage device comprising a memory, a method comprising:

performing a first bit-error-rate estimation scan (BES) on a scan range in the memory, wherein the BES is performed using a first offset;

determining whether a page in the scan range comprises DAC shifts below a criterion; and

in response to determining that the page in the scan range comprises DAC shifts below the criterion, performing a second BES on the page, wherein the second BES is performed using a second offset.

13 . The method of claim 12 , further comprising:

determining whether the page in the scan range comprises DAC shifts below the criterion by monitoring syndrome weight versus BES shifts.

14 . The method of claim 12 , further comprising:

determining whether the page in the scan range comprises DAC shifts below the criterion by determining whether the DAC shifts are becoming increasingly negative and out of a range.

15 . The method of claim 12 , further comprising:

Determining whether the page in the scan range comprises DAC shifts below the criterion by determining whether the page comprises an offset based on data-storage-device-level statistics.

16 . The method of claim 12 , wherein the BES comprises BES5, which performs five memory senses.

17 . The method of claim 16 , wherein performing the second BES using the second offset avoids performing BES7, which performs seven memory senses.

18 . The method of claim 12 , wherein the page in the scan range comprises DAC shifts below the criterion in response to a first data retention condition.

19 . The method of claim 12 , wherein the memory comprises multi-level memory cells.

20 . The method of claim 12 , wherein the memory comprises a three-dimensional memory.

Assignments (3)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0486 →
Continuity (1)
Related Publication 20260094660A1 · Apr 2, 2026
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