Method and system for an asynchronous successive approximation register analog-to-digital converter with word completion algorithm
Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors and compare signals at outputs of the switched capacitors. The SAR ADC may also determine, based on a value of a tunable time interval, whether to set a metastability flag for a first bit to be evaluated and update the value of the tunable time interval based on whether the metastability flag was set.
1. A method of operating a successive approximation register (SAR) analog-to-digital converter (ADC), the method comprising:
comparing output signals of a plurality of switched capacitors;
determining, based on a value of a tunable time interval, whether to set a metastability flag for a first bit to be evaluated; and
updating the value of the tunable time interval based on whether the metastability flag was set.
2. The method of claim 1 , further comprising increasing an accumulator value in response to determining that the metastability flag was not set, wherein updating the value of the tunable time interval comprises increasing the value of the tunable time interval in response to determining that the accumulator value reaches an overflow limit.
3. The method of claim 2 , further comprising setting the accumulator value to half of the overflow limit in response to determining that the accumulator value reaches an overflow limit.
4. The method of claim 1 , further comprising decreasing an accumulator value in response to determining that the metastability flag was set, wherein updating the value of the tunable time interval comprises decreasing the value of the tunable time interval in response to determining that the accumulator value reaches zero.
5. The method of claim 4 , further comprising setting the accumulator value to half of an overflow limit in response to determining that the accumulator value reaches zero.
6. The method of claim 1 , further comprising using the metastability flag for word completion.
7. The method of claim 6 , wherein using the metastability flag for word completion comprises extrapolating a second bit based on the first bit and the metastability flag.
8. The method of claim 7 , wherein the first bit is a least significant bit of a plurality of bits and the second bit follows the first bit.
9. The method of claim 7 , wherein the second bit is an exclusive or of the first bit and the metastability flag.
10. The method of claim 1 , wherein the metastability flag is stored in a metastability flag register of the SAR ADC, and wherein the value of the tunable time interval is stored in a time interval tune register of the SAR ADC.
11. A SAR ADC comprising:
a plurality of switched capacitors configured to sample input signals;
a comparator configured to compare output signals from the plurality of switched capacitors; and
a metastability detector configured to:
determine, based on a value of a tunable time interval, whether to set a metastability flag for a first bit to be evaluated; and
update the value of the tunable time interval based on whether the metastability flag was set.
12. The SAR ADC of claim 11 , wherein the metastability detector is further configured to increase an accumulator value in response to determining that the metastability flag was not set, wherein updating the value of the tunable time interval comprises increasing the value of the tunable time interval in response to determining that the accumulator value reaches an overflow limit.
13. The SAR ADC of claim 12 , wherein the metastability detector is further configured to set the accumulator value to half of the overflow limit in response to determining that the accumulator value reaches an overflow limit.
14. The SAR ADC of claim 11 , wherein the metastability detector is further configured to decrease an accumulator value in response to determining that the metastability flag was set, wherein updating the value of the tunable time interval comprises decreasing the value of the tunable time interval in response to determining that the accumulator value reaches zero.
15. The SAR ADC of claim 14 , wherein the metastability detector is further configured to set the accumulator value to half of an overflow limit in response to determining that the accumulator value reaches zero.
16. The SAR ADC of claim 11 , wherein the metastability detector is further configured to use the metastability flag for word completion.
17. The SAR ADC of claim 16 , wherein using the metastability flag for word completion comprises extrapolating a second bit based on the first bit and the metastability flag.
18. The SAR ADC of claim 17 , wherein the first bit is a least significant bit of a plurality of bits and the second bit follows the first bit.
19. The SAR ADC of claim 17 , wherein the second bit is an exclusive or of the first bit and the metastability flag.
20. A SAR ADC comprising:
a comparator configured to compare output signals from a plurality of switched capacitors; and
a metastability detector configured to:
determine, based on a value of a tunable time interval, whether to set a metastability flag for a least significant bit of a plurality of bits;
update the value of the tunable time interval based on whether the metastability flag for the least significant bit was set; and
extrapolating an additional bit as an exclusive or of the least significant bit and the metastability flag of the least significant bit.