IP Library › Granted Patent US 11,887,687

Granted Patent B2

US 11,887,687 · App. 17/652,233 · Granted Jan 30, 2024

Read operations for a memory array and register

Inventor: Vijayakrishna J. Vankayala (Allen, TX)

Assignee: Micron Technology, Inc.

G11C7/1039 G11C7/109 G11C7/1012 G11C7/1063 G11C7/1066 G11C7/1093

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 11,887,687
App. No.: 17/652,233
Granted: Jan 30, 2024
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Methods, systems, and devices for read operations for a memory array and register are described. In some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). The memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). Because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.

Claims (66)

1. A memory device, comprising:

a memory array comprising a plurality of memory cells configured to store first data, wherein the first data is output from the memory array based at least in part on the memory device receiving a first command;

a first buffer coupled with the memory array and configured to buffer the first data based at least in part on the first data being output from the memory array;

a register configured to store second data, wherein the second data is output from the register based at least in part on the memory device receiving a second command different than the first command;

a second buffer coupled with the register and configured to buffer the second data based at least in part on the second data being output from the register; and

a multiplexer coupled with the first buffer, the second buffer, and a data bus, wherein the multiplexer is configured to output the first data and the second data on the data bus during consecutive sets of clock cycles, wherein a first latency between the memory device receiving the first command and the multiplexer outputting the first data is the same as a second latency between the memory device receiving the second command and the multiplexer outputting the second data.

2. The memory device of claim 1 , further comprising:

a first circuit coupled with the first buffer and configured to receive the first command and output first signaling to the first buffer, wherein the first signaling is associated with a third latency between the memory device receiving the first command and reading the first data from the memory array, and wherein the first buffer is configured to output the first data based at least in part on receiving the first signaling.

3. The memory device of claim 2 , further comprising:

a second circuit coupled with the second buffer and configured to receive the second command and output second signaling to the second buffer, wherein the second signaling is associated with a fourth latency between the memory device receiving the second command and reading the second data from the register, and wherein the second buffer is configured to output the second data based at least in part on receiving the second signaling.

4. The memory device of claim 3 , wherein the first latency between the memory device receiving the first command and the multiplexer outputting the first data is the same as the second latency between the memory device receiving the second command and the multiplexer outputting the second data based at least in part on the first circuit outputting the first signaling and the second circuit outputting the second signaling.

5. The memory device of claim 3 , further comprising:

a latch coupled with the first circuit, the second circuit, and the multiplexer, wherein the latch is configured to output a control signal to the multiplexer based at least in part on receiving the first signaling or the second signaling.

6. The memory device of claim 1 , wherein:

the memory device is configured to receive the first command during a first set of clock cycles and receive the second command during a second set of clock cycles;

the multiplexer is configured to output the first data during a third set of clock cycles and output the second data during a fourth set of clock cycles; and

the consecutive sets of clock cycles comprise the third set of clock cycles and the fourth set of clock cycles.

7. The memory device of claim 6 , wherein a last clock cycle of the first set of clock cycles and a first clock cycle of the second set of clock cycles are consecutive clock cycles.

8. The memory device of claim 7 , wherein:

a last clock cycle of the third set of clock cycles and a first clock cycle of the fourth set of clock cycles are consecutive clock cycles; and

the first set of clock cycles comprises a same quantity of clock cycles as the third set of clock cycles.

9. The memory device of claim 6 , wherein a fifth set of clock cycles occurs between a last clock cycle of the first set of clock cycles and a first clock cycle of the second set of clock cycles.

10. The memory device of claim 9 , wherein:

the first set of clock cycles comprises a different quantity of clock cycles than the third set of clock cycles; and

the fifth set of clock cycles comprises a same quantity of clock cycles as a difference in the quantity between the first set of clock cycles and the third set of clock cycles.

11. The memory device of claim 1 , wherein:

the second command is received by the memory device before the first command; and

the multiplexer is configured to output the first data before outputting the second data.

12. A memory device of comprising:

a first buffer coupled with the memory array and configured to buffer the first data based at least in part on the first data being output from the memory array, wherein the first buffer comprises a first-in first-out (FIFO) buffer having a first depth;

a second buffer coupled with the register and configured to buffer the second data based at least in part on the second data being output from the register, the second buffer comprising a FIFO buffer having a second depth different than the first depth, wherein a buffer depth is associated with a quantity of data bursts that a respective buffer can store during a duration; and

13. A method, comprising:

receiving, during a first set of clock cycles, a first command for reading first data of a memory array of a memory device, wherein the memory device comprises the memory array and a register associated with one or more parameters for operation of the memory device;

receiving a second command for reading second data of the register of the memory device during a second set of clock cycles; and

outputting the first data from the memory array and the second data from the register via a data bus coupled with the memory array and the register based at least in part on receiving the first command and the second command, wherein the first data is output from the memory array during a third set of clock cycles and the second data is output from the register during a fourth set of clock cycles, and wherein a last clock cycle of the third set of clock cycles and a first clock cycle of the fourth set of clock cycles are consecutive clock cycles, and

wherein a first latency between receiving the first command and outputting the first data is the same as a second latency between receiving the second command and outputting the second data.

14. The method of claim 13 , wherein a last clock cycle of the first set of clock cycles and a first clock cycle of the second set of clock cycles are consecutive clock cycles.

15. The method of claim 14 , wherein the first set of clock cycles comprises a same quantity of clock cycles as the third set of clock cycles.

16. The method of claim 13 , wherein a fifth set of clock cycles occurs between a last clock cycle of the first set of clock cycles and a first clock cycle of the second set of clock cycles.

17. The method of claim 16 , wherein:

the first set of clock cycles comprises a different quantity of clock cycles than the third set of clock cycles; and

the fifth set of clock cycles comprises a same quantity of clock cycles as a difference in the quantity between the first set of clock cycles and the third set of clock cycles.

18. The method of claim 13 , wherein:

the second command is received before the first command; and

the first data is output from the memory array before the second data is output from the register.

19. An apparatus, comprising:

a memory array;

a register coupled with the memory array, wherein the register is associated with one or more parameters for operation of the memory array;

a data bus coupled with the memory array and the register; and

a controller coupled with the memory array and the register, wherein the controller is operable to cause the apparatus to:

receive, during a first set of clock cycles, a first command for reading first data of the memory array;

receive a second command for reading second data of the register during a second set of clock cycles; and

output the first data from the memory array and the second data from the register via the data bus coupled with the memory array and the register based at least in part on receiving the first command and the second command, wherein the first data is output from the memory array during a third set of clock cycles and the second data is output from the register during a fourth set of clock cycles, and wherein a last clock cycle of the third set of clock cycles and a first clock cycle of the fourth set of clock cycles are consecutive clock cycles, and

wherein a first latency between receiving the first command and outputting the first data is the same as a second latency between receiving the second command and outputting the second data.

20. The apparatus of claim 19 , wherein a last clock cycle of the first set of clock cycles and a first clock cycle of the second set of clock cycles are consecutive clock cycles.

21. The apparatus of claim 20 , wherein the first set of clock cycles comprises a same quantity of clock cycles as the third set of clock cycles.

22. The apparatus of claim 19 , wherein a fifth set of clock cycles occurs between a last clock cycle of the first set of clock cycles and a first clock cycle of the second set of clock cycles.

23. The apparatus of claim 22 , wherein:

the first set of clock cycles comprises a different quantity of clock cycles than the third set of clock cycles; and

the fifth set of clock cycles comprises a same quantity of clock cycles as a difference in the quantity between the first set of clock cycles and the third set of clock cycles.

24. The apparatus of claim 19 , wherein:

the second command is received before the first command; and

the first data is output from the memory array before the second data is output from the register.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2022

From: VANKAYALA, VIJAYAKRISHNA J.

To: MICRON TECHNOLOGY, INC.

Reel/Frame 059199/0555 →

Continuity (1)

Related Publication 20230267974A1 · Aug 24, 2023