IP Library › Granted Patent US 12,160,994
Granted Patent B2
US 12,160,994 · App. 17/652,308 · Granted Dec 3, 2024

Memory device with ferroelectric layer

Inventors: Tsunehiro Ino (Fujisawa, JP); Akira Takashima (Fuchu, JP)
Assignee: Kioxia Corporation
H10B51/30H01L29/516H01L29/78391H10B51/20
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Quick Facts
Patent No.
US 12,160,994
App. No.
17/652,308
Granted
Dec 3, 2024
Kind
B2
Abstract

A memory device according to an embodiment includes a semiconductor layer, a gate electrode layer, and a first dielectric layer provided between the semiconductor layer and the gate electrode layer. The first dielectric layer contains aluminum (Al), a first element, nitrogen (N), and silicon (Si). The first element is at least one element selected from the group consisting of scandium (Sc), yttrium (Y), lanthanoid (Ln), boron (B), gallium (Ga), and indium (In).

Claims (25)

1. A memory device comprising:

a semiconductor layer;

a gate electrode layer; and

a first dielectric layer provided between the semiconductor layer and the gate electrode layer, the first dielectric layer containing aluminum (Al), a first element, nitrogen (N), and silicon (Si), the first element being at least one element selected from the group consisting of scandium (Sc), yttrium (Y), lanthanoid (Ln), boron (B), gallium (Ga), and indium (In), wherein

when the first dielectric layer contains oxygen (O), an atomic concentration of oxygen in the first dielectric layer is lower than an atomic concentration of aluminum (Al) in the first dielectric layer, the atomic concentration of oxygen in the first dielectric layer is lower than an atomic concentration of the first element in the first dielectric layer, the atomic concentration of oxygen in the first dielectric layer is lower than an atomic concentration of nitrogen (N) in the first dielectric layer, and the atomic concentration of oxygen in first dielectric layer is lower than an atomic concentration of silicon (Si) in the first dielectric layer.

2. The memory device according to claim 1 , wherein the first dielectric layer has a thickness of equal to or less than 30 nm.

3. The memory device according to claim 1 , wherein the atomic concentration of the first element in the first dielectric layer is lower than the atomic concentration of the aluminum (Al) in the first dielectric layer.

4. The memory device according to claim 1 , wherein the atomic concentration of the first element in the first dielectric layer is equal to or more than 5% and equal to or less than 20%.

5. The memory device according to claim 1 , wherein a ratio of the atomic concentration of the nitrogen (N) in the first dielectric layer to a sum of respective atomic concentrations of the aluminum (Al), the first element, and the silicon (Si) in the first dielectric layer is equal to or more than 0.85 and equal to or less than 0.95.

6. The memory device according to claim 1 , wherein the atomic concentration of the silicon (Si) in the first dielectric layer is lower than the atomic concentration of the aluminum (Al) in the first dielectric layer.

7. The memory device according to claim 1 , further comprising: a second dielectric layer provided between the semiconductor layer and the first dielectric layer, the second dielectric layer containing at least either silicon (Si) or nitrogen (N).

8. The memory device according to claim 7 , wherein a thickness of the second dielectric layer is thinner than a thickness of the first dielectric layer.

9. The memory device according to claim 7 , wherein the first dielectric layer includes a first region and a second region provided between the first region and the semiconductor layer, and an atomic concentration of the silicon (Si) in the first region is lower than an atomic concentration of the silicon (Si) in the second region.

10. The memory device according to claim 1 , further comprising a third dielectric layer provided between the first dielectric layer and the gate electrode layer, the third dielectric layer containing at least either silicon (Si) or nitrogen (N).

11. The memory device according to claim 1 , wherein the first dielectric layer contains a wurtzite type crystal.

12. The memory device according to claim 11 , wherein a direction of a c-axis of the wurtzite type crystal falls within a range of +10 degrees with respect to a direction connecting the semiconductor layer and the gate electrode layer.

13. The memory device according to claim 1 , wherein the first dielectric layer is a ferroelectric.

14. A memory device comprising:

a semiconductor layer;

a gate electrode layer;

a first dielectric layer provided between the semiconductor layer and the gate electrode layer, the first dielectric layer containing aluminum (Al), a first element, and nitrogen (N), the first element being at least one element selected from the group consisting of scandium (Sc), yttrium (Y), lanthanoid (Ln), boron (B), gallium (Ga), and indium (In); and

a second dielectric layer provided between the semiconductor layer and the first dielectric layer, the second dielectric layer containing at least either silicon (Si) or nitrogen (N). wherein

when the first dielectric layer contains oxygen (O), an atomic concentration of oxygen in the first dielectric layer is lower than an atomic concentration of aluminum (Al) in the first dielectric layer, the atomic concentration of oxygen in the first dielectric layer is lower than an atomic concentration of the first element in the first dielectric layer, and the atomic concentration of oxygen in the first dielectric layer is lower than an atomic concentration of nitrogen (N) in the first dielectric layer.

15. The memory device according to claim 14 , wherein the first dielectric layer has a thickness of equal to or less than 30 nm.

16. The memory device according to claim 14 , further comprising: a third dielectric layer provided between the first dielectric layer and the gate electrode layer, the third dielectric layer containing at least either silicon (Si) or nitrogen (N).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2022
From: INO, TSUNEHIRO; TAKASHIMA, AKIRA
To: KIOXIA CORPORATION
Reel/Frame 059087/0989 →
Priority Claims (1)
JP 2021-151982 · Sep 17, 2021 · national
Continuity (1)
Related Publication 20230085754A1 · Mar 23, 2023
Cited By (1)
US 12,701,713