Short net pin alignment for routing
Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.
1. A method for providing enhanced routing in a computing environment by one or more processors comprising:
aligning two or more of a plurality of short nets in a cell of an integrated circuit for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold, wherein the aligning pertains to the two-pin net of respective short nets of the two or more short nets, and wherein at least two short nets of the plurality of short nets have their pins aligned using an integer linear program (“ILP”) operation.
2. The method of claim 1 , further including aligning a pair of gate pins for the two or more short nets using a heuristic operation.
3. The method of claim 1 , wherein the at least two short nets of the plurality of short nets have their pins aligned using the ILP operation simultaneously.
4. The method of claim 1 , further including identifying one or more alignment constraints for aligning the two or more of the plurality of short nets.
5. The method of claim 1 , further including generating an alignment graph for aligning the two or more of a plurality of short nets, wherein each node of the alignment graph represents a row segment and indicates a number of gates associated with the node.
6. The method of claim 5 , further including:
identifying one or more subgraphs of the alignment graph, wherein a number of gates associated with each subgraph is less than a threshold.
7. The method of claim 1 , further including:
aligning a remaining set of the plurality of short nets using a heuristic operation, wherein the remaining set of the plurality of short nets does not include the at least two short nets aligned using the ILP operation.
8. A system for providing enhanced routing in a computing environment in a computing environment, comprising:
one or more computers with executable instructions that when executed cause the system to:
align two or more of a plurality of short nets in a cell of an integrated circuit for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold, wherein the aligning pertains to the two-pin net of respective short nets of the two or more short nets, and wherein at least two short nets of the plurality of short nets have their pins aligned using an integer linear program (“ILP”) operation.
9. The system of claim 8 , wherein the executable instructions when executed cause the system to align a pair of gate pins for the two or more short nets using a heuristic operation.
10. The system of claim 8 , wherein the at least two short nets of the plurality of short nets have their pins aligned using the ILP operation simultaneously.
11. The system of claim 8 , wherein the executable instructions when executed cause the system to identify one or more alignment constraints for aligning the two or more of the plurality of short nets.
12. The system of claim 8 , wherein the executable instructions when executed cause the system to generate an alignment graph for aligning the two or more of a plurality of short nets, wherein each node of the alignment graph represents a row segment and indicates a number of gates associated with the node.
13. The system of claim 12 , wherein the executable instructions when executed cause the system to identify one or more subgraphs of the alignment graph, wherein a number of gates associated with each subgraph is less than a threshold.
14. The system of claim 8 , wherein the executable instructions when executed cause the system to:
align a remaining set of the plurality of short nets using a heuristic operation, wherein the remaining set of the plurality of short nets does not include the at least two short nets aligned using the ILP operation.
15. A computer program product for providing enhanced routing in a computing environment in a computing environment, the computer program product comprising:
one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instruction comprising:
program instructions to align one or more of a plurality of short nets in a cell of an integrated circuit for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold, wherein the aligning pertains to the two-pin net of respective short nets of the one or more short nets; and
program instructions to generate an alignment graph for aligning the one or more of the plurality of short nets, wherein each node of the alignment graph represents a row segment and indicates a number of gates associated with the node.
16. The computer program product of claim 15 , wherein a pair of gate pins for the one or more short nets is aligned using a heuristic operation.
17. The computer program product of claim 15 , wherein a plurality of gate pin pairs of the plurality of short nets in the cell of the integrated circuit are aligned using an integer linear program (“ILP”) operation, wherein the one or more short nets are aligned simultaneously.
18. The computer program product of claim 15 , further including program instructions to identify one or more alignment constraints for aligning the one or more of a plurality of short nets.
19. The computer program product of claim 15 , further including program instructions to:
align a first set of the plurality of short nets using an integer linear program (“ILP”) operation; and
align a remaining set of the plurality of short nets using a heuristic operation.
20. The computer program product of claim 15 , further including program instructions to identify one or more subgraphs of the alignment graph, wherein a number of gates associated with each subgraph is less than a threshold.