Bipolar transistor structure on semiconductor fin and methods to form same

1. A bipolar transistor structure comprising:

a semiconductor fin on a substrate, the semiconductor fin having a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction;

a first emitter/collector (E/C) material between and contacting a first sidewall of a first spacer horizontally adjacent the first E/C material and a first sidewall of the semiconductor fin, the first E/C material being along the width of the semiconductor fin, and the first E/C material having a second doping type opposite the first doping type and having a first width;

a second E/C material between and contacting a first sidewall of a second spacer horizontally adjacent the second E/C material and a second sidewall of the semiconductor fin, the second E/C material being along the width of the semiconductor fin, and the second E/C material having the second doping type and having a second width different from the first width of the first E/C material;

an insulator layer separating the first and second E/C materials from the substrate, wherein the insulator layer contacts a portion of the first and second sidewalls of the semiconductor fin, a second sidewall of the first spacer, and a second sidewall of the second spacer,

wherein a horizontal distance between the first sidewall of the semiconductor fin and the first spacer is different than a horizontal distance between the second sidewall of the semiconductor fin and the second spacer, and wherein a top surface of the first spacer and a top surface of the second spacer extend above a top surface of the semiconductor fin.

2. The bipolar transistor structure of claim 1 , further comprising a complementary metal oxide semiconductor (CMOS) device on the substrate and horizontally distal to the semiconductor fin.

3. The bipolar transistor structure of claim 1 , further comprising a trench isolation (TI) adjacent a lower portion of the semiconductor fin, wherein the first E/C material and the second E/C material are over the TI.

4. The bipolar transistor structure of claim 3 , further comprising an air gap vertically between the TI and the first E/C material or the second E/C material.

5. The bipolar transistor structure of claim 1 , wherein the semiconductor fin includes:

an extrinsic base region in a first portion of the semiconductor fin; and

an intrinsic base region in a second portion of the semiconductor fin adjacent the first portion along the length of the semiconductor fin, and horizontally between the first E/C material and the second E/C material along the width of the semiconductor fin, wherein the intrinsic base region has a lower dopant concentration than a dopant concentration of the extrinsic base region.

6. The bipolar transistor structure of claim 5 , wherein the semiconductor fin includes an intermediate portion between the first portion and the second portion along the length of the semiconductor fin, wherein the intermediate portion has a lower dopant concentration than the dopant concentration of the intrinsic base region.

7. A bipolar transistor structure comprising:

a semiconductor fin on a substrate, the semiconductor fin having a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction, wherein the semiconductor fin includes:

a first portion, and

a second portion coupled to a base contact and adjacent the first portion along the length of the semiconductor fin, wherein a dopant concentration of the second portion is greater than a dopant concentration of the first portion;

a first emitter/collector (E/C) material between and contacting a first sidewall of a first spacer horizontally adjacent the first E/C material and a first sidewall of the second portion, the first E/C material being along the width of the semiconductor fin, and the first E/C material having a second doping type opposite the first doping type and having a first width; and

a second E/C material between and contacting a first sidewall of a second spacer horizontally adjacent the second E/C material and a second sidewall of the second portion, the second E/C material being along the width of the semiconductor fin, and the second E/C material having the second doping type and having a second width different from the first width of the first E/C material;

an insulator layer separating the first and second E/C materials from the substrate, wherein the insulator layer contacts a portion of the first and second sidewalls of the semiconductor fin, a second sidewall of the first spacer, and a second sidewall of the second spacer,

wherein a horizontal distance between the first sidewall of the semiconductor fin and the first spacer is different than a horizontal distance between the second sidewall of the semiconductor fin and the second spacer, and wherein a top surface of the first spacer and a top surface of the second spacer extend above a top surface of the semiconductor fin.

8. The bipolar transistor structure of claim 7 , further comprising a complementary metal oxide semiconductor (CMOS) device on the substrate and horizontally distal to the semiconductor fin.

9. The bipolar transistor structure of claim 7 , further comprising a trench isolation (TI) adjacent a lower portion of the semiconductor fin, wherein the first E/C material and the second E/C material are over the TI.

10. The bipolar transistor structure of claim 9 , further comprising an air gap vertically between the TI and the first E/C material or the second E/C material.

11. The bipolar transistor structure of claim 7 , wherein the semiconductor fin includes an intermediate portion between the first portion and the second portion along the length of the semiconductor fin, wherein the intermediate portion has a lower dopant concentration than the dopant concentration of the first portion and the dopant concentration of the second portion.

12. The bipolar transistor structure of claim 11 , further comprising a masking material over the semiconductor fin, and horizontally between the first E/C material and the second E/C material along the width of the semiconductor fin.

13. A method of forming a bipolar transistor structure, the method comprising:

forming a semiconductor fin on a substrate, the semiconductor fin having a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction;

forming an insulator layer on the substrate;

forming a first emitter/collector (E/C) material adjacent a first sidewall of the semiconductor fin along the width of the semiconductor fin, the first E/C material having a second doping type opposite the first doping type;

forming a second E/C material adjacent a second sidewall of the semiconductor fin along the width of the semiconductor fin, the second E/C material having the second doping type,

wherein a width of the first E/C material is different from a width of the second E/C material;

forming a first spacer over the substrate and horizontally distal to the first sidewall of the semiconductor fin, wherein a first sidewall of the first spacer contacts the first E/C material; and

forming a second spacer over the substrate and horizontally distal to the second sidewall of the semiconductor fin, wherein a first sidewall of the second spacer contacts the second E/C material, and wherein a top surface of the first spacer and a top surface of the second spacer extend above a top surface of the semiconductor fin,

wherein the insulator layer separates the first and second E/C materials from the substrate, wherein the insulator layer contacts a portion of the first and second sidewalls of the semiconductor fin, a second sidewall of the first spacer, and a second sidewall of the second spacer, and

wherein a first horizontal distance between the first sidewall of the semiconductor fin and the first spacer is different than a second horizontal distance between the second sidewall of the semiconductor fin and the second spacer, the first horizontal distance defines a first width of the first E/C material, and the second horizontal distance defines a second width of the second E/C material different from the first width of the first E/C material, and

wherein the first E/C material contacts and extends between the first sidewall of the semiconductor fin and the first spacer, and wherein the second E/C material contacts and extends between the second sidewall of the semiconductor fin and the second spacer.

14. The method of claim 13 , further comprising forming a complementary metal oxide semiconductor (CMOS) device on the substrate and horizontally distal to the semiconductor fin.

15. The method of claim 13 , further comprising forming a trench isolation (TI) adjacent a lower portion of the semiconductor fin, wherein the first E/C material and the second E/C material are over the TI.

16. The method of claim 15 , wherein forming the first E/C material and the second E/C material includes forming an air gap vertically between the TI and the first E/C material or the second E/C material.

17. The method of claim 13 , further comprising:

forming an extrinsic base region in a first portion of the semiconductor fin; and

forming an intrinsic base region in a second portion of the semiconductor fin adjacent the first portion along the length of the semiconductor fin, and horizontally between the first E/C material and the second E/C material along the width of the semiconductor fin, wherein the intrinsic base region has a lower dopant concentration than a dopant concentration of the extrinsic base region.