Dual chip clock synchronization

1. A method comprising:

setting a first clock of a first semiconductor circuit and a second clock of a second semiconductor circuit to a common clock source when both the first and second semiconductor circuits are in a slow clock speed, wherein an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating at the slow clock speed;

synchronizing a first division counter of the first clock and a second division counter of the second clock at the slow clock speed; and

simultaneously switching both the first and second semiconductor circuits to a fast clock speed that is a multiple of the slow clock speed, wherein the IO is not capable of operating at the fast clock speed.

2. The method of claim 1 , further comprising:

using a pulse of the first division counter to shadow the first division counter to a third division counter on the second semiconductor circuit; and

comparing the third division counter to the second division counter.

3. The method of claim 1 , further comprising deskewing a clock mesh of both the first and second semiconductor circuit at the slow clock speed.

4. The method of claim 1 , further comprising deskewing a clock mesh of both the first and second semiconductor circuit at the fast clock speed.

5. The method of claim 2 , wherein the pulse is sent periodically from the first division counter at specific predetermined numeric states of the first division counter.

6. The method of claim 2 , further comprising:

detecting a difference between the third division counter and the second division counter;

stopping functional logical of the second semiconductor circuit;

aligning the second division counter and the third division counter while the functional logical is stopped; and

restarting the functional logical once the second division counter is aligned with the third division counter, such that each of the second division counter and the third division counter and the first division counter are all synchronized.

7. The method of claim 6 , wherein data content is frozen for a few cycles as the functional logical is stopped and restarted once the first and second division counters are synchronized such that data content is maintained rather than lost.

8. The method of claim 6 , wherein a state machine of the second semiconductor circuit is running while the functional logical is stopped.

9. A system comprising:

a first semiconductor circuit that includes a first clock and a first division counter and is configured to execute operations at both a slow clock speed and a fast clock speed, wherein the fast clock speed is an even multiple of the slow clock speed;

a second semiconductor circuit that includes a second clock and a second division counter and is configured to execute operations at both the slow clock speed and the fast clock speed; and

an input/output (IO) at an interface between the first and second semiconductor circuit that is capable of operating at the slow clock speed but not the fast clock speed, wherein the first and second semiconductor circuit are configured to:

set the first and second clock a common clock source when the first and second semiconductor circuits are in the slow clock speed;

synchronize the first and second division counters at the slow clock speed; and

simultaneously switch to the fast clock speed.

10. The system of claim 9 , wherein the first and second semiconductor circuit are further configured to:

use a pulse of the first division counter to shadow the first division counter to a third division counter on the second semiconductor circuit; and

compare the third division counter to the second division counter.

11. The system of claim 9 , wherein the first and second semiconductor circuit are further configured to deskew a clock mesh of both the first and second semiconductor circuit at the slow clock speed.

12. The system of claim 9 , wherein the first and second semiconductor circuit are further configured to deskew deskewing a clock mesh of both the first and second semiconductor circuit at the fast clock speed.

13. The system of claim 10 , wherein the pulse is sent periodically from the first division counter at specific predetermined numeric states of the first division counter.

14. The system of claim 13 , wherein the first and second semiconductor circuit are further configured to:

detect a difference between the third division counter and the second division counter;

stop functional logical of the second semiconductor circuit;

align the second division counter and the third division counter while the functional logical is stopped; and

restart the functional logical once the second division counter is aligned with the third division counter, such that each of the second division counter and the third division counter and the first division counter are all synchronized.

15. The system of claim 14 , wherein data content is frozen for a few cycles as the functional logical is stopped and restarted once the first and second division counters are synchronized such that data content is maintained rather than lost.

16. The system of claim 14 , wherein a state machine of the second semiconductor circuit is running while the functional logical is stopped.

17. A method comprising:

setting a first clock of a first semiconductor circuit and a second clock of a second semiconductor circuit to a common clock source when both the first and second semiconductor circuits are in a slow clock speed, wherein an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating at the slow clock speed;

synchronizing a first division counter of the first clock and a second division counter of the second clock at the slow clock speed;

simultaneously switching both the first and second semiconductor circuits to a fast clock speed that is a multiple of the slow clock speed, wherein the IO is not capable of operating at the fast clock speed;

using a pulse of the first division counter to shadow the first division counter to a third division counter on the second semiconductor circuit;

comparing the third division counter to the second division counter;

detecting a difference between the third division counter and the second division counter;

stopping functional logical of the second semiconductor circuit;

aligning the second division counter and the third division counter while the functional logical is stopped; and

restarting the functional logical once the second division counter is aligned with the third division counter, such that each of the second division counter and the third division counter and the first division counter are all synchronized.

18. The method of claim 17 , wherein the pulse is sent periodically from the first division counter at specific predetermined numeric states of the first division counter.

19. The method of claim 17 , wherein data content is frozen for a few cycles as the functional logical is stopped and restarted once the first and second division counters are synchronized such that data content is maintained rather than lost.

20. The method of claim 17 , further comprising:

deskewing a clock mesh of both the first and second semiconductor circuit at the slow clock speed; and

deskewing a clock mesh of both the first and second semiconductor circuit at the fast clock speed.