FinFET device and method of forming same

1. A method comprising:

forming a semiconductor structure over a substrate;

forming a dummy gate structure over the semiconductor structure;

removing a portion of the semiconductor structure adjacent the dummy gate structure to form a first recess;

forming a stressor material in the first recess, wherein the stressor material comprises a dielectric material;

forming one or more dielectric layers over the stressor material;

after forming the one or more dielectric layers, etching the one or more dielectric layers and at least a portion of the stressor material, wherein the etching exposes a sidewall of the semiconductor structure in the first recess; and

after etching the stressor material, epitaxially growing a source/drain region in the first recess.

2. The method of claim 1 , wherein forming the stressor material comprises:

depositing a first dielectric stress layer in the first recess; and

depositing a second dielectric stress layer over the first dielectric stress layer.

3. The method of claim 2 , wherein forming the stressor material further comprises:

after depositing the first dielectric stress layer and prior to depositing the second dielectric stress layer, annealing the first dielectric stress layer.

4. The method of claim 2 , wherein forming the stressor material further comprises:

after depositing the second dielectric stress layer, annealing the second dielectric stress layer.

5. The method of claim 2 , wherein depositing the first dielectric stress layer comprises depositing a first material using a first set of process parameters, wherein depositing the second dielectric stress layer comprises depositing the first material using a second set of process parameters, wherein the first set of process parameters is different than the second set of process parameters.

6. The method of claim 5 , wherein the first material comprises silicon nitride.

7. The method of claim 1 , wherein the one or more dielectric layers comprise an etch stop layer and an interlayer dielectric layer over the etch stop layer.

8. The method of claim 7 , wherein etching the one or more dielectric layers removes the interlayer dielectric layer from the etch stop layer along a sidewall of the dummy gate structure.

9. A method comprising:

patterning a substrate to form a strip, the strip comprising a first semiconductor material;

forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above a top surface of the isolation region;

forming a gate structure along sidewalls and along a first top surface of the upper portion of the strip;

performing a first etching process on the strip to form a first recess in the strip adjacent to the gate structure;

forming a first dielectric material within the first recess, the first dielectric material exerting a stress to a channel region in the strip;

removing the first dielectric material from the first recess using multiple separate etch processes; and

epitaxially growing a source/drain region in the first recess.

10. The method of claim 9 , wherein the gate structure is a dummy gate structure, and further comprising after forming the source/drain region, replacing the dummy gate structure with a replacement gate structure.

11. The method of claim 9 , wherein forming the first dielectric material comprises:

depositing a dielectric material; and

annealing the dielectric material.

12. The method of claim 9 , wherein forming the first dielectric material comprises depositing the first dielectric material within the first recess and over the gate structure, further comprising, prior to epitaxially growing the source/drain region, forming one or more dielectric layers over the gate structure and at least a portion of the first dielectric material, wherein removing the first dielectric material comprises:

prior to forming the one or more dielectric layers, performing a first etch process to remove the first dielectric material from over the gate structure; and

after forming the one or more dielectric layers, performing a second etch process to remove the first dielectric material from the first recess.

13. The method of claim 9 , wherein forming the first dielectric material comprises:

depositing a plurality of layers of the first dielectric material; and

performing at least a first anneal after depositing a first layer of the plurality of layers and prior to depositing a final layer of the plurality of layers.

14. The method of claim 13 , wherein forming the first dielectric material further comprises performing a second anneal after depositing the final layer of the plurality of layers.

15. The method of claim 13 , wherein depositing the first layer of the plurality of layers uses different process conditions than depositing the final layer of the plurality of layers.

16. A method comprising:

forming a first dummy gate structure over a semiconductor structure, the semiconductor structure protruding above an isolation region on a substrate;

forming a first recess in the semiconductor structure adjacent the first dummy gate structure;

forming a dielectric stressor material in the first recess;

forming a dielectric layer over the dielectric stressor material;

forming an opening in the dielectric layer, the opening exposing exposed portions of the dielectric stressor material;

after forming the opening, removing the exposed portions of the dielectric stressor material to expose a channel region; and

after removing the exposed portions of the dielectric stressor material, epitaxially growing a source/drain material in the first recess.

17. The method of claim 16 , further comprising forming a buffer layer, wherein the dielectric stressor material is formed over the buffer layer.

18. The method of claim 17 , further comprising after removing the exposed portions of the dielectric stressor material, removing at least a portion of the buffer layer.

19. The method of claim 16 , wherein forming the dielectric stressor material comprises forming a plurality of dielectric layers and performing a plurality of anneals.

20. The method of claim 16 , wherein a portion of the dielectric stressor material remains in the first recess after epitaxially growing the source/drain material in the first recess.