Method of forming source/drain regions with quadrilateral layers
A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.
1. A method comprising:
forming a protruding semiconductor stack comprising:
a plurality of sacrificial layers; and
a plurality of nanostructures, wherein the plurality of sacrificial layers and the plurality of nanostructures are laid out alternatingly;
forming a dummy gate structure on the protruding semiconductor stack;
etching the protruding semiconductor stack to form a source/drain recess; and
forming a first source/drain region comprising:
growing first epitaxial layers in the source/drain recess, wherein the first epitaxial layers are grown on sidewalls of the plurality of nanostructures, wherein a cross-section of each of the first epitaxial layers has a quadrilateral shape, and wherein the first epitaxial layers have a first dopant concentration; and
forming a second epitaxial layer on the first epitaxial layers, wherein the second epitaxial layer has a second dopant concentration higher than the first dopant concentration.
2. The method of claim 1 , wherein the protruding semiconductor stack is formed over a semiconductor substrate having a {110} surface orientation.
3. The method of claim 1 , wherein the cross-section of each of the first epitaxial layers has a rectangular shape.
4. The method of claim 1 , wherein each of the first epitaxial layers comprises:
a first sidewall contacting one of the plurality of nanostructures; and
a second sidewall opposite to the first sidewall, wherein the first sidewall and the second sidewall are parallel to each other.
5. The method of claim 4 , wherein the first sidewall and the second sidewall of the each of the first epitaxial layers have (110) surface orientations.
6. The method of claim 1 , wherein each of the first epitaxial layers comprises:
a top surface at a top surface level, a bottom surface at a bottom surface level, and a middle level in middle between the top surface level and the bottom surface level; and
a top thickness measured at the top surface level, a bottom thickness measured at the bottom surface level, and a middle thickness measured at the middle level, wherein the top thickness, the bottom thickness, and the middle thickness are equal to each other.
7. The method of claim 1 , wherein when the first source/drain region is formed, a second source/drain region is formed on an opposite side of the protruding semiconductor stack than the first source/drain region, and wherein a direction pointing from the first source/drain region to the second source/drain region is a [110] lattice direction of the plurality of nanostructures.
8. The method of claim 1 , wherein the growing the first epitaxial layers comprises growing SiAs.
9. The method of claim 1 , wherein the growing the first epitaxial layers comprises growing SiCP.
10. A method comprising:
forming a plurality of nanostructures, with upper nanostructures in the plurality of nanostructures overlapping lower nanostructures in the plurality of nanostructures;
forming a first source/drain region comprising:
epitaxially growing first epitaxial layers on sidewalls of the plurality of nanostructures, wherein a cross-section of each of the first epitaxial layers has a quadrilateral shape, and wherein the first epitaxial layers have a first dopant concentration; and
epitaxially growing a second epitaxial layer on the first epitaxial layers, wherein the second epitaxial layer has a second dopant concentration higher than the first dopant concentration; and
forming a gate stack comprising portions between the plurality of nanostructures.
11. The method of claim 10 , wherein the plurality of nanostructures are formed over a semiconductor substrate having a {110} surface orientation.
12. The method of claim 10 , wherein one of the plurality of nanostructures comprises:
a top surface at a top surface level, a bottom surface at a bottom surface level, and a middle level between the top surface level and the bottom surface level, and wherein one of the first epitaxy layers contacting the one of the plurality of nanostructures comprises:
a top thickness measured at the top surface level;
a bottom thickness measured at the bottom surface level; and
a middle thickness measured at the middle level, wherein the top thickness, the bottom thickness, and the middle thickness are equal to each other.
13. The method of claim 10 , wherein the cross-section of one of the first epitaxial layers is grown as having a rectangular shape.
14. The method of claim 10 , wherein the cross-section of one of the first epitaxial layers is grown as having a trapezoid shape.
15. The method of claim 10 further comprising forming a second source/drain region on an opposite side of the plurality of nanostructures than the first source/drain region, wherein a direction pointing from the first source/drain region to the second source/drain region is in a [110] lattice direction of the plurality of nanostructures.
16. The method of claim 10 , wherein the first epitaxial layers comprise SiAs or SiCP, and the second epitaxial layer comprise SiP, and wherein the second epitaxial layer is doped to a higher dopant concentration than the first epitaxial layers.
17. A method comprising:
forming a plurality of semiconductor layers, with upper semiconductor layers in the plurality of semiconductor layers overlapping lower semiconductor layers in the plurality of semiconductor layers, wherein each of the plurality of semiconductor layers comprises:
a top surface at a top surface level;
a bottom surface at a bottom surface level; and
a middle level between the top surface level and the bottom surface level;
forming a gate stack extending into spaces between the plurality of semiconductor layers; and
forming a first source/drain region comprising:
forming first epitaxial layers on sidewalls of the plurality of semiconductor layers, wherein each of the first epitaxial layers is formed as having:
a top thickness measured at the top surface level of one of the plurality of semiconductor layers;
a bottom thickness measured at the bottom surface level of the one of the plurality of semiconductor layers; and
a middle thickness measured at a middle surface level in middle of the top surface level and the bottom surface level, wherein the top thickness, the bottom thickness, and the middle thickness are substantially equal to each other; and
forming a second epitaxial layer on the first epitaxial layers, wherein the second epitaxial layer is doped with a second dopant concentration different than a first dopant concentration of the first epitaxial layers.
18. The method of claim 17 , wherein the top thickness, the bottom thickness, and the middle thickness are equal to each other.
19. The method of claim 17 , wherein a cross-section of each of the first epitaxial layers has a trapezoid shape.
20. The method of claim 17 further comprising forming inner spacers between the plurality of semiconductor layers, wherein one of the first epitaxial layers further contacts one of the inner spacers.