IP Library Granted Patent US 12,051,661
Granted Patent B2
US 12,051,661 · App. 17/658,232 · Granted Jul 30, 2024

Oxidation and corrosion prevention in semiconductor devices and semiconductor device assemblies

Inventors: Srinivasa Reddy Yeduru (Fishkill, NY); George Chang (Tempe, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L24/05H01L24/03H01L24/37H01L24/45H01L2224/035H01L2224/05582H01L2224/05624H01L2224/05639H01L2224/05647H01L2224/05655H01L2224/05666H01L2924/365
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Quick Facts
Patent No.
US 12,051,661
App. No.
17/658,232
Granted
Jul 30, 2024
Kind
B2
Abstract

In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.

Claims (41)

1. An electronic device comprising:

a substrate;

a metallization layer, the metallization layer having:

a first surface disposed on the substrate;

a second surface opposite the first surface; and

a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer, the corrosion-prevention implant layer including at least one of aluminum or magnesium; and

an electrical connector coupled with the second surface.

2. The electronic device of claim 1 , wherein the substrate includes a semiconductor device.

3. The electronic device of claim 1 , wherein:

the substrate includes a ceramic substrate; and

the metallization layer is direct-bonded to the ceramic substrate.

4. The electronic device of claim 1 , wherein the metallization layer includes a copper metallization layer.

5. The electronic device of claim 1 , wherein the metallization layer includes one of an aluminum metallization layer, an aluminum-copper metallization layer, a titanium-nickel-copper metallization layer, or a titanium-nickel-silver metallization layer.

6. The electronic device of claim 1 , wherein the electrical connector includes one of a conductive clip, or a bond wire.

7. The electronic device of claim 1 , wherein:

the thickness of the metallization layer is greater than or equal to 1 micrometer; and

the depth of the corrosion-prevention implant layer is less than or equal to 100 nanometers.

8. The electronic device of claim 1 , wherein the depth of the corrosion-prevention implant layer is less than or equal to ten percent of the thickness of the metallization layer.

9. The electronic device of claim 1 , wherein the corrosion-prevention implant layer is:

disposed in a first portion of the metallization layer that is coupled with the electrical connector; and

excluded from a second portion of the metallization layer, the second portion being different than the first portion.

10. A semiconductor device comprising:

a semiconductor substrate;

a top level metallization layer disposed on the semiconductor substrate;

a passivation layer including an opening, the opening exposing a surface of a portion of the top level metallization layer;

a corrosion-prevention implant layer disposed in the portion of the top level metallization layer, the corrosion-prevention implant layer extending from the exposed surface to a depth from the exposed surface in the top level metallization layer, the depth being less than a thickness of the top level metallization layer, the corrosion-prevention implant layer including at least one of aluminum or magnesium; and

an electrical connector coupled with the exposed surface.

11. The semiconductor device of claim 10 , wherein the top level metallization layer includes a copper metallization layer.

12. The semiconductor device of claim 10 , wherein the top level metallization layer includes one of an aluminum metallization layer, an aluminum-copper metallization layer, or a titanium-nickel-silver metallization layer.

13. The semiconductor device of claim 10 , wherein the electrical connector includes one of a conductive clip, or a bond wire.

14. The semiconductor device of claim 10 , wherein:

the thickness of the top level metallization layer is greater than or equal to 1 micrometer; and

the depth of the corrosion-prevention implant layer is less than or equal to 100 nanometers.

15. The semiconductor device of claim 10 , wherein the depth of the corrosion-prevention implant layer is less than or equal to ten percent of the thickness of the top level metallization layer.

16. A method for producing an electronic device, the method comprising:

forming a metallization layer on a substrate, the metallization layer having:

a first surface disposed on the substrate; and

a second surface opposite the first surface;

forming a corrosion-prevention implant layer in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer, the corrosion-prevention implant layer including at least one of aluminum or magnesium; and

coupling an electrical connector with the second surface.

17. The method of claim 16 , wherein the electrical connector includes one of a conductive clip, or a bond wire.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 061071, FRAME 052 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, AS GRANTOR; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC., AS GRANTOR
Reel/Frame 064067/0654 →
SECURITY INTEREST Recorded Aug 4, 2022
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 061071/0525 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2022
From: YEDURU, SRINIVASA REDDY; CHANG, GEORGE
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 059532/0081 →