IP Library Granted Patent US 11,901,184
Granted Patent B2
US 11,901,184 · App. 17/659,068 · Granted Feb 13, 2024

Backmetal removal methods

Inventors: Michael J. Seddon (Gilbert, AZ); Francis J. Carney (Phoenix, AZ); Chee Hiong Chew (Seremban, MY); Soon Wei Wang (Seremban, MY); Eiji Kurose (Oizumi-machi, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/302H01L21/48H01L21/561H01L21/565H01L21/78H01L23/12H01L23/3185H01L24/04H01L24/26B32B43/006H01L21/784H01L2224/94Y10T156/1158Y10T156/1917
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Quick Facts
Patent No.
US 11,901,184
App. No.
17/659,068
Granted
Feb 13, 2024
Kind
B2
Abstract

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Claims (36)

1. A method of forming a semiconductor package, the method comprising:

forming a plurality of notches into a first side of a semiconductor substrate;

thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches;

stress relief etching the second side of the semiconductor substrate;

applying a backmetal over the second side of the semiconductor substrate;

removing one or more portions of the backmetal through jet ablation; and

singulating the semiconductor substrate through the plurality of notches into a plurality of semiconductor packages.

2. The method of claim 1 , further comprising forming a die support structure within the plurality of notches.

3. The method of claim 2 , wherein forming the die support structure within the plurality of notches further comprises forming one of a permanent die support structure, a temporary die support structure, or any combination thereof comprising a perimeter comprising a closed shape.

4. The method of claim 3 , wherein the one of the permanent die support structure, the temporary die support structure, or any combination thereof comprises two or more layers.

5. The method of claim 2 , further comprising forming a second die support structure coupled to the second side of the semiconductor substrate.

6. The method of claim 1 , wherein a perimeter of each of a plurality of semiconductor die comprised in the semiconductor substrate each comprises a closed shape.

7. A method of forming a semiconductor package, the method comprising:

forming a plurality of notches into a first side of a semiconductor substrate;

thinning a second side of the semiconductor substrate opposite the first side to the plurality of notches;

applying a backmetal over the second side of the semiconductor substrate;

removing one or more portions of the backmetal through jet ablation; and

singulating the semiconductor substrate into a plurality of semiconductor packages.

8. The method of claim 7 , further comprising forming a die support structure in the plurality of notches.

9. The method of claim 8 , wherein the die support structure is formed through a molding process.

10. The method of claim 8 , further comprising forming a second die support structure coupled to the second side of the semiconductor substrate.

11. The method of claim 8 , wherein the die support structure comprises two or more layers.

12. The method of claim 7 , wherein a perimeter of each of a plurality of semiconductor die comprised in the semiconductor substrate each comprises a closed shape.

13. The method of claim 7 , further comprising forming a plurality of electrical connectors on the first side of the semiconductor substrate.

14. A method of forming a semiconductor package, the method comprising:

forming a die support structure over a first side of a semiconductor substrate and a plurality of notches in the semiconductor substrate;

thinning a second side of a semiconductor substrate opposite the first side toward the plurality of notches to expose the die support structure in the plurality of notches;

applying a backmetal over the second side of the semiconductor substrate;

removing one or more portions of the backmetal through jet ablation; and

singulating the semiconductor substrate into a plurality of semiconductor packages.

15. The method of claim 14 , wherein the plurality of notches are die streets between a plurality of die comprised on the semiconductor substrate.

16. The method of claim 14 , wherein a perimeter of each of a plurality of semiconductor die comprised in the semiconductor substrate each comprises a closed shape.

17. The method of claim 14 , wherein forming a die support structure over the first side of the semiconductor substrate further comprises forming one of a permanent die support structure, a temporary die support structure, or any combination thereof comprising a perimeter comprising a closed shape.

18. The method of claim 17 , further comprising forming one of a second permanent die support structure or a second temporary die support structure coupled to the second side of the semiconductor substrate.

19. The method of claim 17 , wherein the one of the permanent die support structure, the temporary die support structure, or any combination thereof comprises two or more layers.

20. The method of claim 14 , further comprising forming a plurality of electrical connectors on the first side of the semiconductor substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 061071, FRAME 052 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, AS GRANTOR; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC., AS GRANTOR
Reel/Frame 064067/0654 →
SECURITY INTEREST Recorded Aug 4, 2022
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 061071/0525 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2022
From: SEDDON, MICHAEL J.; CARNEY, FRANCIS J.; CHEW, CHEE HIONG; WANG, SOON WEI; KUROSE, EIJI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 059585/0493 →