Image sensors having dielectric relaxation correction circuitry
Some image sensors include pixels with capacitors. The capacitor may be used to store charge in the imaging pixel before readout. The capacitor may be a metal-insulator-metal (MIM) capacitor that is susceptible to dielectric relaxation. Dielectric relaxation may cause lag in the signal on the capacitor that impacts the signal on the capacitor during sampling. The image sensor may include dielectric relaxation correction circuitry that leverages the linear relationship between voltage stress and lag signal to correct for dielectric relaxation. The image sensor may include shielded pixels that operate with a similar timing scheme as the imaging pixels in the active array. Measured lag signals from the shielded pixels may be used to correct imaging data.
1. An image sensor comprising:
an array of imaging pixels that is exposed to incident light;
shielded pixels that are shielded from the incident light, wherein each one of the imaging pixels and shielded pixels includes a capacitor, and wherein the shielded pixels are configured to:
obtain a lag signal measurement by applying a first voltage stress to the capacitor; and
obtain a reference measurement by applying a second voltage stress to the capacitor.
2. The image sensor defined in claim 1 , wherein applying the first voltage stress to the capacitor comprises applying the first voltage stress to the capacitor before an integration time.
3. The image sensor defined in claim 2 , wherein applying the second voltage stress to the capacitor comprises applying the second voltage stress to the capacitor after the integration time.
4. The image sensor defined in claim 1 , further comprising:
circuitry configured to quantify an effect of a lag signal using a difference between the lag signal measurement and the reference measurement.
5. The image sensor defined in claim 1 , further comprising:
circuitry configured to determine a difference between the lag signal measurement and the reference measurement.
6. The image sensor defined in claim 1 , further comprising:
dielectric relaxation compensation circuitry that is configured to compensate raw pixel data from the array of imaging pixels for lag using the lag signal measurement and the reference measurement.
7. The image sensor defined in claim 1 , further comprising:
dielectric relaxation compensation circuitry that is configured to, using the lag signal measurement and the reference measurement, compensate for steady state effects of lag, wherein the dielectric relaxation compensation circuitry does not include a frame buffer.
8. The image sensor defined in claim 1 , further comprising:
dielectric relaxation compensation circuitry that is configured to, using the lag signal measurement and the reference measurement, compensate for transient effects of lag, wherein the dielectric relaxation compensation circuitry includes a frame buffer.
9. An image sensor comprising:
an array of imaging pixels that is exposed to incident light, wherein each imaging pixel includes a capacitor;
shielded pixels that are shielded from the incident light and that are configured to generate test signals; and
dielectric relaxation correction circuitry that does not include a frame buffer, wherein the dielectric relaxation correction circuitry is configured to, using the test signals, correct raw pixel data from the imaging pixels for steady state effects of lag caused by dielectric relaxation in the capacitors of the imaging pixels.
10. The image sensor defined in claim 9 , wherein the dielectric relaxation correction circuitry is configured to determine a relationship between lag and voltage stress using the test signals.
11. The image sensor defined in claim 9 , wherein each one of the shielded pixels has a respective capacitor with a respective bottom plate coupled to a driver.
12. The image sensor defined in claim 9 , wherein the array of imaging pixels is operated with a first timing scheme that includes a stress time, a float time, and a reset time and wherein the shielded pixels are operated with a second timing scheme that also includes the stress time, the float time, and the reset time.
13. The image sensor defined in claim 9 , wherein the array of imaging pixels is operated with an integration time of a first duration, wherein the shielded pixels generate a test signal while voltage stress is applied to a capacitor in each one of the shielded pixels for a stress time, and wherein the stress time has a second duration.
14. The image sensor defined in claim 13 , wherein the second duration is the same as the first duration.
15. The image sensor defined in claim 13 , wherein the second duration is within a factor of 3 of the first duration.
16. The image sensor defined in claim 9 , wherein each shielded pixel has the same component arrangement as the array of imaging pixels.
17. The image sensor defined in claim 9 , wherein correcting the raw pixel data from the imaging pixels for steady state effects of lag comprises assuming that data values for a given frame are the same as data values for a previous frame to the given frame.
18. An image sensor comprising:
an array of imaging pixels that is exposed to incident light, wherein each imaging pixel includes a capacitor;
shielded pixels that are shielded from the incident light and that are configured to generate test signals; and
dielectric relaxation correction circuitry that includes a frame buffer, wherein the dielectric relaxation correction circuitry is configured to, using data from at least one previous frame, correct raw pixel data from the imaging pixels for effects of lag caused by dielectric relaxation in the capacitors of the imaging pixels.
19. The image sensor defined in claim 18 , wherein each one of the shielded pixels has the same component arrangement as the array of imaging pixels.
20. The image sensor defined in claim 18 , wherein the array of imaging pixels is operated with a first timing scheme that includes a stress time, a float time, and a reset time and wherein the shielded pixels are operated with a second timing scheme that also includes the stress time, the float time, and the reset time.