Multiple partitions in a data processing array

1. An apparatus, comprising:

a data processing array having a plurality of array tiles;

wherein each array tile includes a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile;

wherein each adjacent memory interface of each array tile includes isolation logic that is programmable to prevent the circuitry disposed within the adjacent array tile from accessing the RAM via the adjacent memory interface; and

wherein the data processing array is subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.

2. The apparatus of claim 1 , wherein:

a first array tile is disposed in a first partition of the plurality of partitions, wherein the first array tile includes a first RAM and a first adjacent memory interface for the RAM;

a second array tile is disposed in a second partition of the plurality of partitions, wherein the second array tile is adjacent to the first array tile and includes a core coupled to the first adjacent memory interface; and

wherein isolation logic of the first adjacent memory interface is programmed to prevent the core from accessing the first RAM of the first array tile.

3. The apparatus of claim 1 , wherein:

a first array tile is disposed in a first partition of the plurality of partitions, wherein the first array tile includes a first RAM and a first adjacent memory interface for the RAM;

a second array tile disposed in a second partition of the plurality of partitions, wherein the second array tile is adjacent to the first array tile and includes a direct memory access circuit coupled to the first adjacent memory interface; and

wherein isolation logic of the first adjacent memory interface is programmed to prevent the direct memory access circuit from accessing the first RAM of the first array tile.

4. The apparatus of claim 1 , further comprising:

a plurality of clock gate circuits, wherein each clock gate circuit is programmable to selectively gate a clock signal provided to a respective one of the plurality of partitions.

5. The apparatus of claim 4 , wherein the clock signal directed to each partition is derived from a different clock signal.

6. The apparatus of claim 4 , further comprising:

a plurality of switches, wherein each switch receives a plurality of different clock signals and is programmable to output a selected clock signal selected from the plurality of different clock signals to a respective one of the plurality of clock gate circuits.

7. The apparatus of claim 6 , wherein each switch of the plurality of switches is programmable at runtime of the data processing array to output different ones of the plurality of different clock signals received by the switch.

8. The apparatus of claim 1 , wherein each partition is a separate power domain that may be powered on and off independently of other ones of the plurality of partitions.

9. The apparatus of claim 8 , wherein each partition has a separate and independent power source.

10. The apparatus of claim 8 , wherein at least two of the power domains have power sources of different voltages.