Logarithmic amplifiers in silicon microphones
A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.
1. A logarithmic amplifier comprising:
a plurality of programmable gain amplifiers each having a different gain, wherein an input of each of the plurality of programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and
a summing circuit having a plurality of inputs coupled to a corresponding output of each of the plurality of programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit is configured for generating a plurality of piecewise linear segments, wherein the summing circuit comprises a switched capacitor circuit.
2. The logarithmic amplifier of claim 1 , wherein the switched capacitor circuit comprises a plurality of switched capacitors each switched between a corresponding programmable gain amplifier output and a summing node of the summing circuit.
3. The logarithmic amplifier of claim 1 , wherein an input of the summing circuit comprises a transconductance circuit.
4. A circuit comprising:
a piecewise linear amplifier comprising a plurality of programmable gain amplifiers, the piecewise linear amplifier having an input for receiving an analog input voltage;
an analog-to-digital converter (ADC) having an input coupled to an output of the piecewise linear amplifier; and
a digital anti-logarithmic component coupled to an output of the ADC, wherein an output of the digital anti-logarithmic component provides a linearized digital signal corresponding to the analog input voltage.
5. The circuit of claim 4 , wherein the piecewise linear amplifier comprises a switched capacitor piecewise linear amplifier.
6. The circuit of claim 4 , wherein the piecewise linear amplifier comprises a continuous time piecewise linear amplifier.
7. The circuit of claim 4 , wherein the ADC comprises a sigma-delta ADC.
8. The circuit of claim 4 , wherein a size of the ADC is inversely proportional to a number of the programmable gain amplifiers in the piecewise linear amplifier.
9. The circuit of claim 4 , wherein the digital anti-logarithmic component comprises:
a first gain path and a second gain path coupled to an input of the digital anti-logarithmic component; and
a multiplexer coupled to the first gain path and the second gain path, and an output forming an output of the digital anti-logarithmic component.
10. The circuit of claim 9 , wherein the digital anti-logarithmic component further comprises:
an absolute value component coupled to the input of the digital anti-logarithmic component; and
a comparator having a first input coupled to the absolute value component, a second input for receiving a reference voltage, and an output coupled to the output of the digital anti-logarithmic component.
11. The circuit of claim 4 , wherein the analog input voltage comprises an analog voltage generated by a MEMS device.
12. A method comprising:
amplifying an analog input signal in a plurality of parallel gain paths, wherein each of the parallel gain paths comprises a different gain value;
generating a plurality of charges from a plurality of output voltages of the parallel gain paths, wherein generating the plurality of charges comprises generating the plurality of charges in a switched capacitor circuit; and
summing the plurality of currents or charges to provide a piecewise linear output voltage approximating a logarithmic output voltage.
13. The method of claim 12 , wherein each of the parallel gain paths saturates at a different analog input signal value.
14. The method of claim 12 , further comprising converting the piecewise linear output voltage into a digital signal.
15. The method of claim 14 , further comprising using an anti-log transfer function component to generate a linearized digital signal output signal corresponding to the analog input signal.
16. A circuit comprising:
a plurality of programmable gain amplifiers each having a different gain, wherein an input of each of the plurality of programmable gain amplifiers is coupled to an input of the circuit;
a summing circuit having a plurality of inputs coupled to a corresponding output of each of the plurality of programmable gain amplifiers and an output coupled to an output of the circuit, wherein the summing circuit is configured for generating a plurality of piecewise linear segments; and
an anti-logarithmic component coupled to an output of the summing circuit, wherein an output of the anti-logarithmic component provides a linearized signal corresponding to an analog input signal at the input of the circuit.
17. The circuit of claim 16 , further comprising an analog-to-digital converter (ADC) coupled between the summing circuit and the anti-logarithmic component, wherein the anti-logarithmic component comprises a digital circuit, and the linearized signal comprises a digital linearized signal.
18. The circuit of claim 16 , wherein the summing circuit comprises a switched capacitor circuit.
19. The circuit of claim 16 , wherein the summing circuit comprises a resistor circuit.
20. The circuit of claim 19 , wherein the resistor circuit comprises a plurality of resistors each coupled between a corresponding programmable gain amplifier output and a summing node of the summing circuit.