Non-conformal gate oxide formation on FinFET
A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.
1. A method comprising:
forming a protruding semiconductor fin protruding higher than isolation regions;
depositing a dummy gate dielectric layer on the protruding semiconductor fin, wherein the dummy gate dielectric layer comprises:
a top portion overlapping the protruding semiconductor fin; and
a sidewall portion on a sidewall of the protruding semiconductor fin, wherein the top portion is thicker than the sidewall portion;
depositing a dummy gate electrode layer over the dummy gate dielectric layer;
patterning the dummy gate electrode layer, wherein a remaining portion of the dummy gate electrode layer forms a dummy gate electrode of a dummy gate stack;
forming gate spacers on opposing sidewalls of the dummy gate stack;
removing the dummy gate electrode to form a trench;
removing a portion of the dummy gate dielectric layer exposed to the trench; and
forming a replacement gate stack in the trench.
2. The method of claim 1 , wherein the protruding semiconductor fin is in a wafer, and the depositing the dummy gate dielectric layer is performed using a production tool comprising:
a top plate;
a bottom plate underlying the top plate, wherein the wafer is placed between the top plate and the bottom plate; and
a negative voltage source, wherein the negative voltage source supplies a negative voltage to the bottom plate during the depositing the dummy gate dielectric layer.
3. The method of claim 2 , wherein the production tool further comprises:
a Radio Frequency (RF) power source acting as the negative voltage source, wherein the RF power source supplies an RF power to the bottom plate during the depositing the dummy gate dielectric layer.
4. The method of claim 3 , wherein the RF power source provides a power lower than about 200 watts.
5. The method of claim 2 , wherein a DC voltage source acts as the negative voltage source, wherein a negative end of the DC voltage source is connected to the bottom plate during the depositing the dummy gate dielectric layer.
6. The method of claim 1 , wherein after the patterning the dummy gate electrode layer, the top portion of the dummy gate dielectric layer remains on top of the protruding semiconductor fin, and the gate spacers are formed overlapping the top portion of the dummy gate dielectric layer.
7. The method of claim 1 , wherein after the patterning the dummy gate electrode layer, the top portion of the dummy gate dielectric layer is etched-through to form a dummy gate dielectric, and the gate spacers contact sidewalls of the dummy gate dielectric.
8. The method of claim 1 further comprising, after the removing the dummy gate electrode to form the trench, performing a plasma oxidation process on a wafer that comprises the protruding semiconductor fin.
9. The method of claim 8 , wherein the plasma oxidation process is performed in a tool with a negative bias provided to a bottom plate underlying the wafer.
10. The method of claim 9 , wherein in the removing the portion of the dummy gate dielectric layer exposed to the trench, an overhang portion of the gate spacers overlapping the portion of the dummy gate dielectric layer is oxidized, and during the removing the portion of the dummy gate dielectric layer, the overhang portion is removed.
11. A method comprising:
forming a dummy gate oxide on a wafer, wherein the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer, wherein the dummy gate oxide is a non-conformal layer including a top portion on the top surface of the protruding semiconductor fin and a sidewall portion on the sidewall of the protruding semiconductor fin, wherein the top portion is thicker than the sidewall portion, wherein the forming the dummy gate oxide comprises a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process comprises applying a Radio Frequency (RF) power to a conductive plate below the wafer;
forming a dummy gate electrode over the dummy gate oxide;
removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers; and
forming a replacement gate in the trench.
12. The method of claim 11 , wherein the applying the RF power comprises connecting an RF power to the conductive plate.
13. The method of claim 12 , wherein the RF power is lower than about 200 watts.
14. The method of claim 11 , wherein the forming the dummy gate oxide comprises depositing silicon oxide.
15. The method of claim 11 , wherein at a time after the dummy gate oxide is removed, portions of the dummy gate oxide remain to be directly underlying the gate spacers, and wherein the portions of the dummy gate oxide comprise a top portion and a sidewall portion thinner than the top portion.
16. The method of claim 11 further comprising performing a plasma oxidation process on the dummy gate oxide.
17. A method comprising:
removing a dummy gate electrode to form a trench between opposing portions of gate spacers, wherein a dummy gate dielectric underlying the dummy gate electrode is exposed, and wherein the dummy gate dielectric has a top portion and a sidewall portion thinner than the top portion;
performing a plasma oxidation process on the opposing portions of the gate spacers;
after the plasma oxidation process, removing the dummy gate dielectric; and
forming a replacement gate stack in the trench.
18. The method of claim 17 , wherein the plasma oxidation process is performed as having both of an isotropic effect and an anisotropic effect.
19. The method of claim 18 , wherein the plasma oxidation process is performed with a negative bias applied underlying a respective wafer that comprising the gate spacers.
20. The method of claim 19 , wherein the negative bias is applied through a RF source.