Image retention mitigation via voltage biasing for organic lighting-emitting diode displays
This document describes systems and techniques for image retention mitigation via voltage biasing for organic light-emitting diode (OLED) displays. In aspects, a pixel array is described having pixel circuits including a first transistor configured to receive a biasing signal from one or more drivers and, based on the biasing signal, enable or disable an application of a bias voltage at a terminal of a second transistor. In so doing, the bias voltage reduces a hysteresis effect experienced by the second transistor for each of the multiple pixel circuits of the pixel array, thereby mitigating an image retention.
1. A display comprising:
a pixel array including multiple pixel circuits, one or more of the multiple pixel circuits comprising:
an organic light-emitting diode (OLED) configured to illuminate;
a first transistor having a first source terminal, a gate terminal, and a first drain terminal, the first transistor configured to receive a first voltage at the source terminal; and
a second transistor having a second source terminal;
an electrical line operably coupled to each of the multiple pixel circuits via the first source terminal, the electrical line configured to transmit the first voltage to the first transistor; and
a scan-line driver operably coupled to each of the multiple pixel circuits via the gate terminal of the first transistor, the scan-line driver configured to:
generate a biasing signal; and
supply the biasing signal to the gate terminal of the first transistor, the biasing signal configured to:
produce a second voltage, based on the first voltage, at the first drain terminal of the first transistor, the second voltage configured to initialize, during a display-frame period, an electrical voltage of the second source terminal of the second transistor to neutralize a voltage stress experienced across the second transistor to reduce a hysteresis effect, effective to mitigate an image retention on the pixel array.
2. The display of claim 1 , wherein one or more of the multiple pixel circuits further comprises:
a third transistor having a second drain terminal electrically coupled to the second source terminal, and wherein the second voltage is configured to initialize, during the display-frame period, a second electrical voltage of the second drain terminal.
3. The display of claim 1 , further comprising one or more pixel circuits not having the first transistor.
4. The display of claim 1 , wherein the biasing signal comprises a voltage configured to cause the organic light-emitting diode to remain dark.
5. The display of claim 1 , wherein the biasing signal comprises a voltage configured to cause the organic light-emitting diode to illuminate a shade of white.