Configurable low ohmic power circuits
A method includes forming a plurality of pockets of semiconductor material in a semiconductor substrate. The plurality of pockets are electrically isolated from the semiconductor substrate. The method further involves forming a metal-oxide-semiconductor field-effect transistor (MOSFET) in a pocket of the plurality of pockets, the MOSFET being a vertical trench shielded gate MOSFET. The method further includes forming an electrical connection to a drain region of the MOSFET vertically below a trench and a mesa of the MOSFET.
1. A semiconductor die, comprising:
a semiconductor material layer having a top surface and a backside surface;
an insulating layer disposed on the backside surface of the semiconductor material layer;
a plurality of insulator-filled trenches extending vertically through a thickness of the semiconductor material layer from the top surface to the insulating layer, the plurality of insulator-filled trenches partitioning the semiconductor material layer into a plurality of pockets, the plurality of insulator-filled trenches defining sidewalls of the plurality of pockets; and
at least one device formed in at least one of the plurality of pockets having a backside contact to a drain region, the backside contact being disposed in an opening in the insulating layer.
2. The semiconductor die of claim 1 , wherein the backside contact to the drain region includes a conductive material disposed in the opening in the insulating layer disposed on the backside surface of the semiconductor material layer.
3. The semiconductor die of claim 1 , wherein the semiconductor material layer includes an epitaxial layer with n-type dopants.
4. The semiconductor die of claim 1 , wherein the at least one device is a first vertical trench metal-oxide semiconductor field effect transistor (MOSFET) disposed in a first pocket from the plurality of pockets, and the semiconductor die further comprises:
a second vertical trench MOSFET disposed in a second pocket from the plurality of pockets.
5. The semiconductor die of claim 1 , wherein the at least one device includes a CMOS device of a controller circuit.
6. The semiconductor die of claim 1 , wherein the at least one device includes a CMOS device of a controller circuit formed in a pocket from the plurality of pockets.
7. The semiconductor die of claim 6 , wherein the opening in the insulating layer provides a backside access to the CMOS device of the controller circuit formed in the pocket from the plurality of pockets.
8. A semiconductor die, comprising:
a semiconductor material layer having a top surface and a backside surface;
a plurality of insulator-filled trenches extending vertically through a thickness of the semiconductor material layer from the top surface to the backside surface, the plurality of insulator-filled trenches partitioning the semiconductor material layer into a plurality of pockets, the plurality of insulator-filled trenches defining sidewalls of the plurality of pockets;
at least one device formed in at least one of the plurality of pockets including a transistor having a backside contact a drain region; and
an insulating layer disposed below the transistor.
9. The semiconductor die of claim 8 , wherein:
the semiconductor material layer includes a p-type doped semiconductor layer disposed on or at the backside surface, an n-type doped layer is disposed on the p-type doped semiconductor layer, and an epitaxial layer with n-type dopants is disposed on the n-type doped layer,
the insulating layer is disposed underneath the p-type doped semiconductor layer on or at the backside surface of the semiconductor material layer, and
the plurality of insulator-filled trenches extend vertically down through a thickness of the semiconductor material layer from the top surface to the p-type doped semiconductor layer disposed on or at the backside surface of the semiconductor material layer, the plurality of pockets being electrically connected to each other by the p-type doped semiconductor layer disposed on or at the backside surface of the semiconductor material layer.
10. The semiconductor die of claim 8 , wherein:
the semiconductor material layer is formed in an epitaxial layer on a substrate of a first conductive type, and a buried conductive layer of a second conductive type is disposed on or at about the backside surface of the semiconductor material layer, and
the plurality of insulator-filled trenches extend vertically down from the top surface to below the buried conductive layer of the second conductive type, the plurality of pockets being electrically isolated from the substrate of the first conductive type in vertical directions by a p-n junction formed between the buried conductive layer of the second conductive type and the substrate of the first conductive type.
11. The semiconductor die of claim 10 , wherein the substrate of the first conductive type is a thinned substrate and a blind through-silicon via (BTSV) extends from a backside of the thinned substrate into at least one of the plurality of pockets.
12. The semiconductor die of claim 11 , wherein the insulating layer is disposed on the backside of the thinned substrate and on sidewalls of the BTSV, and wherein a conductive material deposited in, or deposited on the sidewalls of, the BTSV makes the backside contact through the BTSV to the drain region of the transistor.
13. The semiconductor die of claim 12 , wherein the transistor is a first vertical trench MOSFET in a first pocket from the plurality of pockets, and the semiconductor die further comprises:
a second vertical trench MOSFET in a second pocket from the plurality of pockets.
14. The semiconductor die of claim 8 , wherein:
the semiconductor material layer is formed in an epitaxial silicon layer on a substrate, and a buried layer is disposed on or at about the backside surface of the semiconductor material layer,
the plurality of insulator-filled trenches extend vertically down from the top surface to the backside surface of the semiconductor material layer below the buried layer, the plurality of pockets being electrically isolated from the substrate in vertical directions by a p-n junction formed between the buried layer and the substrate,
the at least one device includes a vertical trench MOSFET fabricated in a pocket of the plurality of pockets, and
at least one conductor extending from a drain terminal on a top side of the pocket down through the pocket to contact the drain region below a plurality of vertical trenches and mesas of the vertical trench MOSFET.
15. The semiconductor die of claim 14 , wherein the at least one conductor extending from the drain terminal on the top side of the pocket down through the pocket passes through a mesa of the plurality of vertical trenches and the mesas of the vertical trench MOSFET formed in the pocket.
16. The semiconductor die of claim 15 , wherein gate poly is disposed asymmetrically in a first trench next to the mesa to have a separation distance from the mesa that is larger than a separation distance from a second mesa adjacent to the first trench.
17. The semiconductor die of claim 15 , wherein gate poly is disposed symmetrically in a first trench next to the mesa to have a separation distance from the mesa that is about a same as a separation distance from a second mesa adjacent to the first trench.
18. A semiconductor die, comprising:
a semiconductor material layer having a top surface and a backside surface;
an insulating layer disposed on the backside surface of the semiconductor material layer;
an insulator-filled trench extending vertically through a thickness of the semiconductor material layer from the top surface to the insulating layer disposed on the backside surface of the semiconductor material layer, the insulator-filled trench partitioning the semiconductor material layer into at least two pockets; and
at least one of the at least two pockets including a transistor having a backside contact to a drain region, the backside contact being disposed in an opening in the insulating layer.
19. The semiconductor die of claim 18 , wherein the backside contact to the drain region includes a conductive material disposed in the opening in the insulating layer disposed on the backside surface of the semiconductor material layer.
20. The semiconductor die of claim 18 , wherein the transistor includes at least one of a complementary metal-oxide semiconductor device of a controller circuit or a vertical trench metal-oxide semiconductor field effect transistor.