Image sensors with hybrid analog-to-digital converter architecture
An image sensor may include an image sensor pixel array, row control circuitry, and column readout circuitry. The column readout circuitry may include analog-to-digital converter (ADC) circuitry. The ADC circuitry may have a first portion that selectively converts pixel signals associated with a low light or high conversion gain operating environment and a second portion that converts any pixel signals. As an example, the first portion may be a ramp ADC and the second portion may be a successive approximation register (SAR) ADC.
1. An image sensor comprising:
a plurality of pixels in an image sensor pixel array;
a conductive line coupled to each of the plurality of pixels; and
analog-to-digital converter circuitry coupled to the plurality of pixels via the conductive line, the analog-to-digital converter circuitry having:
a first analog-to-digital converter coupled to the conductive line,
a second analog-to-digital converter coupled to the conductive line, wherein the second analog-to-digital converter is a successive approximation register analog-to-digital converter, and
a switch having a first terminal coupled to the first analog-to-digital converter and having a second terminal coupled to the second analog-to-digital converter wherein the first and second analog-to-digital converters are analog-to-digital converters of different types.
2. The image sensor defined in claim 1 , wherein the switch is configured to selectively connect the first analog-to-digital converter to the conductive line without disconnecting the second analog-to-digital converter from the conductive line.
3. The image sensor defined in claim 1 , wherein the first analog-to-digital converter is a ramp analog-to-digital converter configured to receive a ramp signal with a full-scale voltage range that is less than a full-scale voltage range of the successive approximation register analog-to-digital converter.
4. The image sensor defined in claim 1 , wherein the successive approximation register analog-to-digital converter includes a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter.
5. The image sensor defined in claim 1 further comprising:
digital data processing circuitry coupled to an output path of the first analog-to-digital converter and coupled to an output path of the second analog-to-digital converter.
6. The image sensor defined in claim 5 , wherein the digital data processing circuitry has an output path configured to provide a digital output corresponding to an analog input on the conductive line.
7. The image sensor defined in claim 5 , wherein the digital data processing circuitry includes an analog-to-digital converter gain adjustment system.
8. The image sensor defined in claim 1 , wherein the plurality of pixels are arranged in a column in the image sensor pixel array, and the conductive line is a column line.
9. The image sensor defined in claim 8 , wherein the analog-to-digital converter circuitry is implemented within column readout circuitry.
10. The image sensor defined in claim 1 , wherein the second analog-to-digital converter remains connected to the conductive line while the first analog-to-digital converter is selectively connected and disconnected to the conductive line.
11. The image sensor defined in claim 1 , wherein the second analog-to-digital converter is configured to process a set of pixel signals from the plurality of pixels and wherein the first analog-to-digital converter is configured to process only a subset of pixel signals in the set of pixel signals.
12. An image sensor comprising:
a plurality of pixels in an image sensor pixel array;
a conductive line coupled to each of the plurality of pixels; and
analog-to-digital converter circuitry coupled to the plurality of pixels via the conductive line, the analog-to-digital converter circuitry having:
a first analog-to-digital converter coupled to the conductive line; and
a second analog-to-digital converter coupled to the column line, the second analog-to-digital converter having a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter.
13. The image sensor defined in claim 12 , wherein the analog-to-digital converter circuitry includes a switch having a first terminal coupled to the first analog-to-digital converter and a second terminal coupled to the second analog-to-digital converter.
14. The image sensor defined in claim 12 , wherein the second analog-to-digital converter is a successive approximation register analog-to-digital converter.
15. The image sensor defined in claim 14 , wherein the successive approximation register analog-to-digital converter includes register logic circuitry operable to control the first and second capacitive digital-to-analog converters.
16. The image sensor defined in claim 14 , wherein the first analog-to-digital converter is a ramp analog-to-digital converter.
17. An image sensor comprising:
an image sensor pixel;
a conductive line coupled to the image sensor pixel;
a first analog-to-digital converter selectively coupled to the conductive line via a switch;
a second analog-to-digital converter connected to the conductive line, wherein the first and second analog-to-digital converters are analog-to-digital converters of different types; and
the switch is configured to selectively disconnect the first analog-to-digital converter from the conductive line and connect the first analog-to-digital converter to the conductive line while the second analog-to-digital converter remains connected to the conductive line.
18. The image sensor defined in claim 17 further comprising:
digital data processing circuitry coupled to the first and second analog-to-digital converters and operable to generate a digital output based on respective outputs from the first and second analog-to-digital converters.
19. The image sensor defined in claim 17 further comprising:
gain adjustment circuitry coupled to the first and second analog-to-digital converters.