Semiconductor device and manufacturing method thereof
A method of manufacturing a semiconductor device includes bonding a first wafer with a second wafer. The second wafer includes a substrate, an isolation structure in the substrate, a transistor on the substrate, and a interconnect structure over the second transistor. A first etching process is performed to form a first via opening and a second via opening in the substrate. The second via opening extends to the isolation structure, and the second via opening is deeper than the first via opening. A second etching process is performed such that the first via opening exposes the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure, and the second via opening penetrates the isolation structure. A first via is formed in the first via opening and a second via is formed in the second via opening.
1 . A semiconductor device, comprising:
a first wafer;
a second wafer bonded to the first wafer, wherein the second wafer comprises:
a substrate;
an isolation structure embedded in the substrate;
a transistor between the substrate and the first wafer; and
an interconnect structure between the transistor and the first wafer;
a first via in a central region of the second wafer and in contact with the interconnect structure; and
a second via in a peripheral region of the second wafer and in contact with the interconnect structure, wherein the isolation structure partially surrounds the second via, the isolation structure is at opposite sides of the second via in a cross-sectional view, and an area of the first via interfacing with the interconnect structure is less than an area of the second via interfacing with the interconnect structure; and
a liner layer wrapped around the second via, wherein the isolation structure is in contact with a first side and a second side of the liner layer in a cross-section view, and the first side is opposite to the second side.
2 . The semiconductor device of claim 1 , wherein the second via is wider than the first via.
3 . The semiconductor device of claim 1 , wherein the first via comprises a first portion and a second portion under the first portion, and the second portion is narrower than the first portion.
4 . The semiconductor device of claim 3 , wherein a height of the second portion of the first via is greater than a height of a source/drain region of the transistor.
5 . The semiconductor device of claim 1 , wherein the liner layer is in contact with both the substrate and the isolation structure.
6 . The semiconductor device of claim 1 , further comprising a dielectric layer over the substrate and surrounds the first via and the second via.
7 . A semiconductor device, comprising:
a first wafer;
a second wafer over the first wafer, wherein the second wafer comprises:
a substrate;
an isolation structure in the substrate;
a first transistor and a second transistor adjacent the isolation structure; and
an interconnect structure between the substrate and the first wafer;
a power via penetrating the substrate and the isolation structure to the interconnect structure, and the isolation structure is at opposite sides of the power via in a cross-sectional view; and
a signal via penetrating the substrate to the interconnect structure, wherein the signal via is between the first transistor and the second transistor but spaced apart from the isolation structure, and an area of the signal via interfacing with the interconnect structure is less than an area of the power via interfacing with the interconnect structure; and
a liner layer wrapped around the power via, wherein the isolation structure is in contact with a first side and a second side of the liner layer in a cross-section view, and the first side is opposite to the second side.
8 . The semiconductor device of claim 7 , wherein the signal via comprises a first portion and a second portion between the first portion and the interconnect structure, and the first portion is wider than the second portion.
9 . The semiconductor device of claim 8 , wherein a top of the second portion is higher than a top of the isolation structure.