Submodule semiconductor package
Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.
1. A semiconductor device comprising:
a die coupled over a lead frame;
a redistribution layer (RDL) coupled over the die;
a first plurality of vias coupled between the RDL and the die; and
a second plurality of vias coupled over and directly to the lead frame, wherein the second plurality of vias are adjacent to an outer edge of the semiconductor device and are electrically isolated from the die.
2. The semiconductor device of claim 1 , wherein a distance between an edge of the RDL and the first plurality of vias is less than 100 micrometers (um).
3. The semiconductor device of claim 1 , wherein a pitch between each via of the first plurality of vias is 235 um.
4. The semiconductor device of claim 1 , wherein the die is coupled in a cavity within the lead frame.
5. The semiconductor device of claim 1 , wherein the RDL is at least 50 um thick.
6. The semiconductor device of claim 1 , wherein the second plurality of vias are arranged in a single row.
7. The semiconductor device of claim 1 , wherein each via of the first plurality of vias comprises a width of at least 150 um.
8. The semiconductor device of claim 1 , wherein an outermost edge of the RDL one of extends to an outer perimeter of the die or is within the outer perimeter of the die.
9. A semiconductor device comprising:
a first die coupled over a lead frame;
a second die coupled over the lead frame;
a first redistribution layer (RDL) coupled over the first die;
a second RDL coupled over the second die;
a first plurality of vias coupled between the first RDL and the first die;
a second plurality of vias coupled between the second RDL and the second die;
a third plurality of vias coupled over and directly to the lead frame, wherein the third plurality of vias are adjacent to an outer side of the semiconductor device and are electrically isolated from the first die and the second die;
a mold compound at least partially encapsulating the first die and the second die; and
a solder mask coupled between the first RDL and the second RDL.
10. The semiconductor device of claim 9 , further comprising a fourth plurality of vias directly coupled over and to the lead frame, wherein the fourth plurality of vias are electrically isolated from the first die and the second die and are adjacent to a second outer side of the semiconductor device opposite the first outer side of the semiconductor device.
11. The semiconductor device of claim 10 , wherein each of the third plurality of vias and the fourth plurality of vias are arranged in a single row.
12. The semiconductor device of claim 9 , wherein the first RDL is entirely within an outer perimeter of the first die and the second RDL is entirely within an outer perimeter of the second die.
13. The semiconductor device of claim 9 , further comprising a third die and a fourth die coupled over the lead frame.
14. The semiconductor device of claim 9 , wherein a distance between an edge of the first RDL and the first plurality of vias is less than 100 um and a distance between an edge of the second RDL and the second plurality of vias is less than 100 um.
15. The semiconductor device of claim 9 , wherein the first plurality of vias are coupled over three separate source pads.
16. A semiconductor package comprising:
a semiconductor device coupled between a first substrate and a second substrate, wherein the semiconductor device comprises:
a die coupled over a lead frame;
a redistribution layer (RDL) coupled over the die;
a first plurality of vias coupled between the RDL and the die; and
a second plurality of vias coupled over and directly to the lead frame;
wherein the second plurality of vias are adjacent to an outer edge of the semiconductor device and are electrically isolated from the die; and
a package lead frame coupled between the first substrate and the second substrate;
wherein the semiconductor device is bonded to the first substrate and the second substrate through a sintering material.
17. The semiconductor package of claim 16 , further comprising a connection pad coupled directly over the die.
18. The semiconductor package of claim 16 , wherein the sintering material comprises a silver sintering material.
19. The semiconductor package of claim 16 , wherein the RDL comprises a plurality of dimples formed therein.
20. The semiconductor package of claim 16 , wherein the second plurality of vias are arranged in a single row.