Semiconductor testing device and method of operating the same
A plurality of devices for testing, connected in series using one or more redistribution layers (RDLs), are used to perform a semiconductor device test on a plurality of dies. As a result, the semiconductor device test may support thousands of gross dies per wafer or greater (e.g., 10,000 dies or greater). Furthermore, the RDL(s) may be removed after use. In some implementations, the devices for testing corresponding to the dies may execute the semiconductor device test sequentially. Accordingly, test data may be generated and may include a bit sequence, where a first bit in the bit sequence indicates an overall outcome for the test and one or more subsequent bits in the bit sequence indicate respective outcomes for each semiconductor dies or for each line of the semiconductor device test.
1. A method, comprising:
forming a plurality of devices for testing on a substrate of a plurality of dies, wherein each die of the plurality of dies is associated with a corresponding one of the plurality of devices for testing;
forming at least one redistribution layer (RDL) over the substrate, the at least one RDL connecting the plurality of devices for testing in series;
performing a circuit probe (CP) test on the plurality of dies using the plurality of devices for testing; and
removing the at least one RDL after the CP test is complete.
2. The method of claim 1 , further comprising:
forming an initial testing module on the substrate connected to the plurality of devices for testing.
3. The method of claim 2 , wherein the initial testing module is formed over a portion of the substrate not including the plurality of dies.
4. The method of claim 2 , further comprising:
removing the initial testing module after the CP test is complete.
5. The method of claim 1 , wherein the at least one RDL comprises one or more materials selected from aluminum, silicon, copper, titanium, tantalum, nitrogen, oxygen, carbon, nickel, cobalt, or tungsten.
6. The method of claim 1 , further comprising:
storing a sequence of bits indicative of results of the CP test, wherein one bit of the sequence of bits is indicative of an overall result and one or more other bits of the sequence of bits are indicative of a die, of the plurality of dies, that is associated with failure.
7. A method, comprising:
performing a circuit probe (CP) test on a substrate of a plurality of dies using a plurality of devices for testing and using one or more redistribution layers (RDLs) that connect the plurality of devices for testing in series, wherein each die of the plurality of dies is associated with a corresponding one of the plurality of devices for testing;
storing a sequence of bits indicative of results of the CP test for the plurality of dies,
wherein an initial bit of the sequence of bits is indicative of an overall result and one or more subsequent bits of the sequence of bits are indicative of which die, of the plurality of dies, is associated with failure; and
removing the one or more RDLs after the CP test is complete.
8. The method of claim 7 , wherein performing the CP test comprises:
connecting a CP test apparatus to an initial testing module; and
transmitting CP test signals using the CP test apparatus.
9. The method of claim 7 , wherein performing the CP test comprises:
connecting a CP test apparatus to a final device for testing of the plurality of devices for testing; and
receiving the sequence of bits using the CP test apparatus.
10. The method of claim 7 , further comprising:
performing an additional CP test on an additional plurality of dies using an additional plurality of devices for testing, wherein each die of the additional plurality of dies is associated with a corresponding one of the additional plurality of devices for testing, and using one or more additional RDLs that connect the plurality of additional devices for testing in series,
wherein the one or more additional RDLs connect the plurality of additional devices for testing in series, separately from the plurality of devices for testing.
11. The method of claim 10 , wherein:
performing the CP test comprises connecting a CP test apparatus to a first initial testing module connected to the plurality of devices for testing; and
performing the additional CP test comprises moving the CP test apparatus to a second initial testing module connected to the additional plurality of devices for testing.
12. The method of claim 7 , further comprising:
forming a plurality of pads, wherein each die of the plurality of dies is associated with a corresponding one of the plurality of pads, based on the sequence of bits.
13. The method of claim 8 , further comprising:
removing the initial testing module after the CP test is complete.
14. A device, comprising:
a plurality of devices for testing formed on a substrate of a plurality of dies,
wherein each die of the plurality of dies is associated with a corresponding one of the plurality of devices for testing, and
wherein the plurality of devices for testing are connected for testing in series;
a plurality of pads, wherein each die of the plurality of dies is associated with a corresponding one of the plurality of pads; and
one or more interconnects between two or more of the plurality of dies, the one or more interconnects being configured to be removed after testing.
15. The device of claim 14 , further comprising:
a plurality of isolation structures between the plurality of dies.
16. The device of claim 14 , further comprising:
a second set of dies on the substrate, wherein the plurality of dies includes a first set of dies; and
a second set of devices for testing formed on the substrate, wherein the plurality of devices for testing includes a first set of devices for testing; and
an additional plurality of pads formed over the second set of dies wherein each die of the second set of dies is associated with a corresponding one of the additional plurality of pads.
17. The device of claim 14 , further comprising:
an initial testing module formed on the substrate and connected to the plurality of devices for testing.
18. The device of claim 17 , wherein the initial testing module is formed over a portion of the substrate not including the plurality of dies.
19. The device of claim 14 , wherein the plurality of devices for testing are connected in series to form a closed loop.
20. The device of claim 14 , wherein the plurality of devices for testing are configured for a circuit probe (CP) test.