IP Library › Granted Patent US 12,189,413
Granted Patent B2
US 12,189,413 · App. 17/665,401 · Granted Jan 7, 2025

Circuits and methods for multi-phase clock generators and phase interpolators

Inventors: Zhaowen Wang (New York, NY); Yudong Zhang (La Jolla, CA); Peter Kinget (Summit, NJ)
Assignee: The Trustees of Columbia University in the City of New York
G06F1/06H03B27/00H03K3/0315H03K5/133H03B2200/0074
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,189,413
App. No.
17/665,401
Granted
Jan 7, 2025
Kind
B2
Abstract

Circuits and methods for multi-phase clock generators and phase interpolators are provided. The multi-phase clock generators include a delay line and multi-phase injection locked oscillator. At each stage of the multi-phase injection locked oscillator, injection currents are provided from a corresponding stage of the delay line. Outputs of the multi-phase injection locked oscillator and provided to mixers which produce inputs to an operational transconductance amplifier which provides feedback to the delay line and the multi-phase injection locked oscillator. The phase interpolator uses a technique of flipping certain input clock signals to reduce the number of components required while still being able to interpolate phase over 360 degrees and to reduce noise.

Claims (84)

1. A circuit for a multi-phase clock generator, comprising:

a delay line comprising a first plurality of differential unit delay cells,

wherein each of the first plurality of differential unit delay cells has a pair of clock inputs and a pair clock outputs,

wherein the first plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the first plurality of differential unit delay cells is connected to the pair of clock inputs of a second of the first plurality of differential unit delay cells, and

wherein each unit cell of the first plurality of differential unit delay cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the first plurality of differential unit delay cells; and

a ring oscillator comprising a second plurality of differential unit delay cells,

wherein each of the second plurality of differential unit delay cells has a pair of clock inputs, a pair of current injection inputs, and a pair clock outputs,

wherein the pair of current injection inputs of each of the second plurality of differential unit delay cells is coupled to the pair of clock outputs of a corresponding one of the first plurality of differential unit delay cells,

wherein the second plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the second plurality of differential unit delay cells is connected to the pair of inputs of a second of the second plurality of differential unit delay cells,

wherein the pair of outputs of a last of the second plurality of differential unit delay cells are flipped and connected to the pair of inputs of a first of the second plurality of differential unit delay cells, and

wherein each unit cell of the second plurality of differential unit cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the second plurality of differential unit delay cells,

wherein the delay line further comprises a dummy unit cell connected to a last of the first plurality of differential unit delay cells.

2. A circuit for a multi-phase clock generator, comprising:

a delay line comprising a first plurality of differential unit delay cells,

wherein each of the first plurality of differential unit delay cells has a pair of clock inputs and a pair clock outputs,

wherein the first plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the first plurality of differential unit delay cells is connected to the pair of clock inputs of a second of the first plurality of differential unit delay cells, and

wherein each unit cell of the first plurality of differential unit delay cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the first plurality of differential unit delay cells; and

a ring oscillator comprising a second plurality of differential unit delay cells,

wherein each of the second plurality of differential unit delay cells has a pair of clock inputs, a pair of current injection inputs, and a pair clock outputs,

wherein the pair of current injection inputs of each of the second plurality of differential unit delay cells is coupled to the pair of clock outputs of a corresponding one of the first plurality of differential unit delay cells,

wherein the second plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the second plurality of differential unit delay cells is connected to the pair of inputs of a second of the second plurality of differential unit delay cells,

wherein the pair of outputs of a last of the second plurality of differential unit delay cells are flipped and connected to the pair of inputs of a first of the second plurality of differential unit delay cells, and

wherein each unit cell of the second plurality of differential unit cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the second plurality of differential unit delay cells,

wherein the pair of current injection inputs of each of the second plurality of differential unit delay cells is coupled to the pair of output of a corresponding one of the first plurality of differential unit delay cells by a buffer.

3. A circuit for a multi-phase clock generator, comprising:

a delay line comprising a first plurality of differential unit delay cells,

wherein each of the first plurality of differential unit delay cells has a pair of clock inputs and a pair clock outputs,

wherein the first plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the first plurality of differential unit delay cells is connected to the pair of clock inputs of a second of the first plurality of differential unit delay cells, and

wherein each unit cell of the first plurality of differential unit delay cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the first plurality of differential unit delay cells; and

a ring oscillator comprising a second plurality of differential unit delay cells,

wherein each of the second plurality of differential unit delay cells has a pair of clock inputs, a pair of current injection inputs, and a pair clock outputs,

wherein the pair of current injection inputs of each of the second plurality of differential unit delay cells is coupled to the pair of clock outputs of a corresponding one of the first plurality of differential unit delay cells,

wherein the second plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the second plurality of differential unit delay cells is connected to the pair of inputs of a second of the second plurality of differential unit delay cells,

wherein the pair of outputs of a last of the second plurality of differential unit delay cells are flipped and connected to the pair of inputs of a first of the second plurality of differential unit delay cells, and

wherein each unit cell of the second plurality of differential unit cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the second plurality of differential unit delay cells,

wherein each unit cell in the first plurality of differential unit delay cells comprises:

a first inverter having an input connected to a first of the pair of clock inputs of the unit cell and having an output connected to a first of the pair of clock outputs of the unit cell;

a second inverter having an input connected to a second of the pair of clock inputs of the unit cell and having an output connected to a second of the pair of clock outputs of the unit cell;

a third inverter having an input connected to the output of the first inverter and having an output connected to the output of the second inverter; and

a fourth inverter having an input connected to the output of the second inverter and having an output connected to the output of the first inverter.

4. A circuit for a multi-phase clock generator, comprising:

a delay line comprising a first plurality of differential unit delay cells,

wherein each of the first plurality of differential unit delay cells has a pair of clock inputs and a pair clock outputs,

wherein the first plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the first plurality of differential unit delay cells is connected to the pair of clock inputs of a second of the first plurality of differential unit delay cells, and

wherein each unit cell of the first plurality of differential unit delay cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the first plurality of differential unit delay cells; and

a ring oscillator comprising a second plurality of differential unit delay cells,

wherein each of the second plurality of differential unit delay cells has a pair of clock inputs, a pair of current injection inputs, and a pair clock outputs,

wherein the pair of current injection inputs of each of the second plurality of differential unit delay cells is coupled to the pair of clock outputs of a corresponding one of the first plurality of differential unit delay cells,

wherein the second plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the second plurality of differential unit delay cells is connected to the pair of inputs of a second of the second plurality of differential unit delay cells,

wherein the pair of outputs of a last of the second plurality of differential unit delay cells are flipped and connected to the pair of inputs of a first of the second plurality of differential unit delay cells, and

wherein each unit cell of the second plurality of differential unit cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the second plurality of differential unit delay cells,

wherein each of the first plurality of differential unit cells also has a pair of current injection inputs.

5. The circuit of claim 4 , wherein the pair of current injection inputs for each of the first plurality of differential unit delay cells is connected to ground.

6. The circuit of claim 3 , wherein each unit cell in the first plurality of differential unit delay cells further comprises:

a first buffer having an input connected to a first of the pair of current injection inputs of the unit cell and having an output connected to the first of the pair of clock outputs of the unit cell; and

a second buffer having an input connected to a second of the pair of current injection inputs of the unit cell and having an output connected to the second of the pair of clock outputs of the unit cell.

7. The circuit of claim 6 , wherein the first buffer is formed from a plurality of selectable, parallel transistors.

8. A circuit for a multi-phase clock generator, comprising:

a delay line comprising a first plurality of differential unit delay cells,

wherein each of the first plurality of differential unit delay cells has a pair of clock inputs and a pair clock outputs,

wherein the first plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the first plurality of differential unit delay cells is connected to the pair of clock inputs of a second of the first plurality of differential unit delay cells, and

wherein each unit cell of the first plurality of differential unit delay cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the first plurality of differential unit delay cells; and

a ring oscillator comprising a second plurality of differential unit delay cells,

wherein each of the second plurality of differential unit delay cells has a pair of clock inputs, a pair of current injection inputs, and a pair clock outputs,

wherein the pair of current injection inputs of each of the second plurality of differential unit delay cells is coupled to the pair of clock outputs of a corresponding one of the first plurality of differential unit delay cells,

wherein the second plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the second plurality of differential unit delay cells is connected to the pair of inputs of a second of the second plurality of differential unit delay cells,

wherein the pair of outputs of a last of the second plurality of differential unit delay cells are flipped and connected to the pair of inputs of a first of the second plurality of differential unit delay cells, and

wherein each unit cell of the second plurality of differential unit cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the second plurality of differential unit delay cells,

wherein at least one unit cell of the first plurality of differential unit delay cells and at least one unit cell of the second plurality of differential unit delay cells include an identical set of components interconnected in an identical manner.

9. The circuit of claim 8 , wherein each unit cell of the second plurality of differential unit delay cells includes an identical set of components interconnected in an identical manner.

10. A circuit for a multi-phase clock generator, comprising:

a delay line comprising a first plurality of differential unit delay cells,

wherein each of the first plurality of differential unit delay cells has a pair of clock inputs and a pair clock outputs,

wherein the first plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the first plurality of differential unit delay cells is connected to the pair of clock inputs of a second of the first plurality of differential unit delay cells, and

wherein each unit cell of the first plurality of differential unit delay cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the first plurality of differential unit delay cells;

a ring oscillator comprising a second plurality of differential unit delay cells,

wherein each of the second plurality of differential unit delay cells has a pair of clock inputs, a pair of current injection inputs, and a pair clock outputs,

wherein the pair of current injection inputs of each of the second plurality of differential unit delay cells is coupled to the pair of clock outputs of a corresponding one of the first plurality of differential unit delay cells,

wherein the second plurality of differential unit delay cells are connected in series such that the pair of clock outputs of a first of the second plurality of differential unit delay cells is connected to the pair of inputs of a second of the second plurality of differential unit delay cells,

wherein the pair of outputs of a last of the second plurality of differential unit delay cells are flipped and connected to the pair of inputs of a first of the second plurality of differential unit delay cells, and

wherein each unit cell of the second plurality of differential unit cells outputs a pair of clock signals having different phases than each pair of clock signals output by other of the second plurality of differential unit delay cells; and

a first mixer that mixes the pairs of outputs of two of the second plurality of differential unit delay cells to produce a first mixer output signal and a second mixer that mixes the pairs of outputs of another two of the second plurality of differential unit delay cells to produce a second mixer output signal.

11. The circuit of claim 10 , further comprising an operation transconductance amplifier that receives the first mixer output signal and the second mixer output signal and produce tuning feedback signal that is provided to the delay line and to the ring oscillator.

12. The circuit of claim 8 , wherein each unit cell of the first plurality of differential unit delay cells has includes an identical set of components interconnected in an identical manner.

Assignments (2)
CONFIRMATORY LICENSE Recorded May 3, 2023
From: COLUMBIA UNIV NEW YORK MORNINGSIDE
To: U.S. DEPARTMENT OF ENERGY
Reel/Frame 063527/0691 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2022
From: WANG, ZHAOWEN; ZHANG, YUDONG; KINGET, PETER
To: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
Reel/Frame 060737/0530 →
Continuity (3)
Provisional Application 63145754 · Feb 4, 2021
Provisional Application 63306898 · Feb 4, 2022
Related Publication 20220244755A1 · Aug 4, 2022
References Cited (41)
US 7456673B2 · Bae et al. · 2008 [cited by applicant]
US 7636411B2 · Canagasaby et al. · 2009 [cited by applicant]
US 7746971B2 · Masui et al. · 2010 [cited by applicant]
US 8487682B2 · Du et al. · 2013 [cited by applicant]
US 8664993B2 · Gu · 2014 [cited by applicant]
US 8718217B2 · Walker et al. · 2014 [cited by applicant]
US 8941420B2 · Zerbe · 2015 [cited by examiner]
US 20200099507A1 · Shinmyo et al. · 2020 [cited by applicant]
Abidi, A.A., “Phase Noise and Jitter in CMOS Ring Oscillators”, In IEEE Journal of Solid-State Circuits, vol. 41, No. 8, Aug. 2006, pp. 1803-1816. [cited by applicant]
Adler, R., “A Study of Locking Phenomena in Oscillators”, In Proceedings of IRE, vol. 34, No. 6, Jun. 1946, pp. 351-357. [cited by applicant]
Auvergne, D., et al., “Signal Transition Time Effect on CMOS Delay Evaluation”, In IEEE Transactions on Circuits System 1, Fundamental Theory Applications, vol. 47, No. 9, Sep. 2000, pp. 1362-1369. [cited by applicant]
Balankutty, A., et al., “Mismatch Characterization of Ring Oscillators”, In Proceedings of IEEE Custom Integrated Circuits Conference, San Jose, CA, US, Sep. 2007, pp. 515-518. [cited by applicant]
Cevrero, A., et al., “6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4/3-Tap NRZ Speculative DFE in 14nm CMOS FinFET”, In IEEE International Solid-State Circuits Conference, Feb. 17-21, 2019, pp. 112-114. [cited by applicant]
Chen, S., et al., “A 4-1o-16GHz Inverter-Based Injection-Locked Quadrature Clock Generator with Phase Interpolators for Multi-Standard I/Os in 7nm FinFET”, In IEEE International Solid-State Circuits Conference, Feb. 11-… [cited by applicant]
Chen, W.C., et al., “A 4-to-18 GHz Active Poly Phase Filter Quadrature Clock Generator wtih Phase Error Correction in 5 nm CMOS”, In Proceedings of IEE Symposium VLSI Circuits, Honolulu, HI, US, Jun. 2020, pp. 1-2. [cited by applicant]
Dunwell, D. and Carusone, A.C., “Modeling Oscillator Injection Locking using the Phase Domain Response”, In IEEE Transactions Circuits System 1 Reg. Papers, vol. 60, No. 11, Nov. 2013, pp. 2823-2833. [cited by applicant]
Elshazly, A., et al., “A 2 GHZ-to7.5 GHz Quadrature Clock-Generator using Digital Delay Locked Loops for Multi-Standard I/Os in 14 nm CMOS”, In Proceedings of the Symposium on VLSI Circuits, Honolulu, HI, US, Jun. 2014,… [cited by applicant]
Errett, M., et al., “A 126 mW 56 GB/s NRZ Wireleline Transceiver for Synchronous Short-Reach Applications in 16 nm FinFET”, In IEEE International Solid-State Circuits Conference Digest Technical Papers, Feb. 2018, pp. 2… [cited by applicant]
Gangasani, G.R., et al., “A 16-Gb/s Backplane Transceiver with 12-Tap Current Integrating DFE and Dynamic Adaption of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology”, In Proceedings of IEEE Custom Integra… [cited by applicant]
Gao, X., et al., “Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops”, In IEEE Transactions on Circuits Systems II, Exp. Briefs, vol. 56, No. 2, Feb. 2009, pp. 117-121. [cited by applicant]
Homayoun, A. and Razavi, B., “Relation between Delay Line Phase Noise and Ring Oscillator Phase Noise”, In IEEE Journal of Solid-State Circuits, vol. 49, No. 2, Feb. 2014, pp. 384-391. [cited by applicant]
Hossain, M., and Carusone, A.C., “CMOS Oscillators for Clock Distribution and Injection-Locked Deskew”, In IEEE Journal of Solid-State Circuits, vol. 44, No. 8, Aug. 2009, pp. 2138-2153. [cited by applicant]
Im, J., et al., “A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET”, In IEEE Journal of Solid-State Circuits, vol. 56, No. 1, … [cited by applicant]
Jeon, M., et al., “A 6-Gbps Dual-Mode Digital Clock and Data Recovery Circuit in a 65-nm CMOS Technology”, In Analog Integrated Circuits Signal Process, vol. 85, Jul. 2015, pp. 209-215. [cited by applicant]
Kabbani, A., et al., “Technology-Portable Analytical Model for DSM CMOS Inverter Transition-Time Estimation”, In IEEE Transactions on Computer Aided Design Integration, vol. 22, No. 9, Sep. 2003, pp. 1177-1187. [cited by applicant]
Kawamoto, T., et al., “3.2 Mutli-Standard 185 fsrms 0.3-to-28 GB/s 40 dB Backplane Signal Conditioner with Adaptive Pattern-Match 36-Tap DFE and Data-Rate-Adjustment PLL in 28 nm CMOS”, In IEEE Internation Solid-State C… [cited by applicant]
Kinget, P., et al., “An Injection-Locking Scheme For Precision Quadrature Generation”, In IEEE Journal of Solid-State Circuits, vol. 37, No. 7, Jul. 2002, pp. 845-851. [cited by applicant]
Kwon, D., et al., “A Clock and Data Recovery Circuit with Programmable Multi-Level Phase Detector Characteristics and a Built-In Jitter Monitor”, In IEEE Transactions on Circuits System 1, vol. 62, No. 6, Jun. 2015, pp.… [cited by applicant]
Mazzanti, A., et al., “A Low-Phase Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers”, In IEEE Journal of Solid-State Circuits, vol. 45, No. 10, Oct. 2010, pp. 2104-211… [cited by applicant]
Mirzaei, A., et al., “Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers”, In IEEE Journal of Solid-State Circuits, vol. 43, No. 3, Feb. 25, 2008, pp. 656-671. [cited by applicant]
Monaco, E., et al., “A 2-11GHz 7-Bit-High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI”, In IEEE Journal of Solid-State Circuits, vol… [cited by applicant]
Navid, R., et al., “A 40Gb/s Serial Link Transceiver in 28 nm CMOS Technology”, In IEEE Journal of Solid-State Circuits, vol. 50, No. 4, Apr. 2015, pp. 814-827. [cited by applicant]
Raj, M., et al., “22.3 A 4-to-11GHz Injection-Locked Quarter-Rate Clocking for an Adaptive 153fJ/b Optical Receiver in 28nm FDSOI CMOS”, In IEEE International Solid-State Circuits Conference, Feb. 22-15, 2015, pp. 404-4… [cited by applicant]
Razavi, B., “A Study of Phase Noise in CMOS Oscillators”, IEEE Journal of Solid-State Circuits, vol. 31, No. 3, Mar. 1996, pp. 331-343. [cited by applicant]
Rodoni, L, et al., “A 5.75 to 44 GB/s Quarter Rate CDR with Data Rate Selection in 90nm Bulk CMOS” In IEEE Journal of Solid-State Circuits, vol. 44, No. 7, Jul. 2009, pp. 1927-1941. [cited by applicant]
Shi, Y., et al., “A Design of Multi-Phase Clocks Generator for CDR”, In Proceedings of the 2016 3rd International Conference on Materials Engineering, Manufacturing Technology and Control, Apr. 2016, pp. 1664-1669. [cited by applicant]
Toifl, T., et al., “A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz Multiphase Generator PLL with 360 degree Digitally Programmable Phase Shift for 10-Gb/s Serial Links”, In IEEE Journal of Solid-State Circuits, vol. 40, No. 12,… [cited by applicant]
Wang, Z., et al., “A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7 GHz Clock Generator in 65 nm with 7 b Phase Interpolators for High-Speed Data Links”, In IEEE International Solid-State Circuits Conference Diges… [cited by applicant]
Won, H., et al., “A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS” In IEEE Journal of Solid-State Circuits, vol. 50, No. 2, Feb. 2015, pp. 399-413. [cited by applicant]
Zhang, B., et al., “A 28 GB/s Multi-Trandard Serial-Link Transceiver for Backplane Applications in 28 nm CMOS”, In IEEE International Solid-State Circuits Conference Digest Technical Papers, Feb. 2015, pp. 1-3. [cited by applicant]
Zhang, Z., et al., “A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator”, In IEEE Journal of Solid State Circuits, vol. 55, No. 10, Jul. 2020,… [cited by applicant]
Cited By (1)
US 12,525,964