Backside integrated voltage regulator for integrated circuits
The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.
1. An integrated circuit (IC) package comprising:
an IC die including a silicon layer; and
an integrated voltage regulator die configured to provide power to the IC die, the integrated voltage regulator being positioned adjacent to the silicon layer and connected to the silicon layer via an intervening power distribution network (PDN).
2. The IC package of claim 1 , wherein the IC package further includes a packaging substrate, wherein the integrated voltage regulator die is connected to the packaging substrate via one or more through mold vias (TMVs) or one or more dielectric vias (TDVs), wherein the integrated voltage regulator die is configured to receive power through the one or more TMVs or TDVs.
3. The IC package of claim 2 , wherein the PDN includes one or more through silicon vias (TSVs) within the silicon layer.
4. The IC package of claim 3 , wherein the PDN further includes a redistribution layer configured to provide power from the integrated voltage regulator die to the TSVs.
5. The IC package of claim 4 , wherein the TSVs and redistribution layer form an inductor.
6. The IC package of claim 2 , wherein each of the one or more TMVs or TDVs are connected to the packaging substrate on a first end by a flip chip bump and to the integrated voltage regulator die at a second opposite end.
7. The IC package of claim 1 , wherein the IC package further includes a packaging substrate, and wherein the silicon layer is connected to the packaging substrate via one or more flip chip bumps.
8. The IC package of claim 1 , wherein the IC package further includes a packaging substrate, and wherein the packaging substrate is configured to connect to a land grid array (LGA) socket or ball grid array (BGA) socket.
9. The IC package of claim 8 , wherein power is delivered to the integrated voltage regulator die via the LGA socket or the BGA socket.
10. The IC package of claim 9 ,
wherein the integrated voltage regulator die is connected to the packaging substrate via one or more through mold vias (TMVs), and
wherein the packaging substrate includes a redistribution layer configured to route the power from the LGA socket or the BGA socket to the one or more TMVs.