IP Library Granted Patent US 12,349,424
Granted Patent B2
US 12,349,424 · App. 17/667,411 · Granted Jul 1, 2025

Epitaxial semiconductor 3D horizontal nano sheet with high mobility 2D material channel

Inventors: Mark I. Gardner (Albany, NY); H. Jim Fulford (Albany, NY); Partha Mukhopadhyay (Albany, NY)
Assignee: Tokyo Electron Limited
H10D62/118H10D30/031H10D30/6713H10D30/6735H10D30/6757H10D84/013H10D84/038
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,349,424
App. No.
17/667,411
Granted
Jul 1, 2025
Kind
B2
Abstract

Methods for the manufacture of semiconductor devices constructed with three-dimensional (3D) horizontal nano sheets with high mobility two-dimensional (2D) material channels are disclosed. Aspects can include forming a semiconductor material; selectively forming a seed material around the bridge; selectively forming a two-dimensional (2D) material around the seed material; forming an active gate around a central portion of the 2D material thereby exposing end portions of the 2D material; and growing source/drain structures coupled to the end portions of the 2D material, respectively.

Claims (34)

1. A device, comprising:

a semiconductor material;

a pair of first dielectric materials in contact with the semiconductor material through only respective ends of the semiconductor material;

a seed material wrapping around the semiconductor material and the pair of first dielectric materials, except sidewalls of the pair of first dielectric materials;

a two-dimensional (2D) material wrapping around the seed material;

an active gate wrapping around the 2D material; and

a pair of source/drain structures in contact with the 2D material.

2. The device of claim 1 , further comprising:

a pair of second dielectric materials coupled to both ends of an upper portion of the active gate; and

a pair of third dielectric materials coupled to both ends of a lower portion of the active gate.

3. The device of claim 2 , wherein the pair of second dielectric materials are configured to electrically isolate at least the upper portion of the active gate from the pair of source/drain structures, and wherein the pair of third dielectric materials are configured to electrically isolate at least the lower portion of the active gate from the pair of source/drain structures.

4. The device of claim 1 , wherein the seed material includes an oxidized portion of the semiconductor material.

5. The device of claim 1 , wherein the active gate comprises:

a high-k dielectric material around a portion of the 2D material; and

a gate metal around a portion of the high-k dielectric material.

6. The device of claim 5 , wherein the portion of the 2D material has a first length and the portion of the high-k dielectric material has a second length, the first length being longer than the second length.

7. The device of claim 1 , further comprising:

a second semiconductor material;

a pair of second dielectric materials in contact with the second semiconductor material through only respective ends of the second semiconductor material;

a second seed material wrapping around the second semiconductor material and the pair of second dielectric materials, except sidewalls of the pair of second dielectric materials;

a second 2D material wrapping around the second seed material;

a second active gate wrapping around the second 2D material; and

a second pair of source/drain structures coupled to the 2D material.

8. The device of claim 7 , wherein the 2D material is an N-type material and the second 2D material is a P-type material.

9. A transistor structure comprising:

a source metal;

a drain metal;

a two-dimensional (2D) channel material partially wrapping around a semiconductor material that extends between the source metal and the drain metal, wherein a first end of the semiconductor material is in contact with only a first dielectric material, and a second end of the semiconductor material is in contact with only a second dielectric material;

a high-k dielectric partially wrapping around the 2D channel material;

a gate metal partially wrapping around the high k-dielectric;

a first dielectric isolating the gate metal from the source metal; and

a second dielectric isolating the gate metal from the drain metal.

10. The transistor structure of claim 9 , further comprising a seed material around the semiconductor material, wherein the 2D channel material is coupled to the seed material.

11. The transistor structure of claim 9 , wherein the source metal and the drain metal are coupled to the 2D channel material and the high-k dielectric material.

Assignments (3)
SECURITY INTEREST Recorded May 20, 2025
From: MY JOB MATCHER, INC.; MJM TECH LIMITED
To: LILY GRACE INVESTMENTS PTY LTD
Reel/Frame 071336/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2022
From: STEWART, ARRAN; O'BRIEN, STEVE
To: MY JOB MATCHER, INC. D/B/A JOB.COM
Reel/Frame 059080/0291 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: GARDNER, MARK I.; FULFORD, H. JIM; MUKHOPADHYAY, PARTHA
To: TOKYO ELECTRON LIMITED
Reel/Frame 058932/0348 →
Continuity (1)
Related Publication 20230253452A1 · Aug 10, 2023
References Cited (9)
US 9024376B2 · Masuoka et al. · 2015 [cited by applicant]
US 9425324B2 · Diaz et al. · 2016 [cited by applicant]
US 9478624B2 · Colinge et al. · 2016 [cited by applicant]
US 20200235098A1 · Li · 2020 [cited by examiner]
US 20200343273A1 · Huang · 2020 [cited by examiner]
US 20220310806A1 · Yang · 2022 [cited by examiner]
US 20220344461A1 · Jung · 2022 [cited by examiner]
US 20230163203A1 · Cheng · 2023 [cited by examiner]
Kai-Shin Li et al., “MoS2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS2 availability,” 2016 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 2016, pp. 1-2… [cited by examiner]