Field-effect transistors including a lower insulating layer
The present disclosure provides a semiconductor device with improved element performance and reliability. The semiconductor device includes a lower insulating layer, a fin-shaped insulating layer that is on the lower insulating layer and extends in a first direction, a field insulating layer that is on the lower insulating layer and extends in the first direction, a plurality of gate structures that are on the fin-shaped insulating layer and include a gate electrode intersecting the fin-shaped insulating layer, a source/drain region that is on the fin-shaped insulating layer and is between the gate structures, and an active pattern that is on the fin-shaped insulating layer and penetrates the gate electrode and is electrically connected to the source/drain region, where the gate electrode extends in a second direction intersecting the first direction.
1. A semiconductor device comprising:
a lower insulating layer;
a fin-shaped insulating layer that is on the lower insulating layer and vertically protrudes upward beyond an upper surface of the lower insulating layer, the fin-shaped insulating layer extending in a first direction;
a field insulating layer that is on the lower insulating layer and extends in the first direction;
a plurality of gate structures that are on the fin-shaped insulating layer and comprise a gate electrode intersecting the fin-shaped insulating layer;
a source/drain region that is on the fin-shaped insulating layer and is between the gate structures; and
an active pattern that is on the fin-shaped insulating layer and penetrates the gate electrode and is electrically connected to the source/drain region,
wherein the gate electrode extends in a second direction intersecting the first direction,
wherein at least a part of the source/drain region overlaps the fin-shaped insulating layer in the first direction, and
wherein a bottom surface of the active pattern is coplanar with or higher than an upper surface of the fin-shaped insulating layer, with the upper surface of the lower insulating layer providing a base reference plane.
2. The semiconductor device of claim 1 , wherein the source/drain region comprises a first source/drain region,
wherein the semiconductor device further comprises a second source/drain region adjacent to the first source/drain region in the second direction, and
wherein a bottom surface of the second source/drain region is higher than a bottom surface of at least one of the gate structures relative to the upper surface of the lower insulating layer.
3. The semiconductor device of claim 1 , wherein the field insulating layer comprises a field liner layer that defines a field recess and a field filling layer that is on the field liner layer and in the field recess.
4. The semiconductor device of claim 3 ,
wherein the field liner layer comprises a horizontal part that defines a bottom surface of the field recess and a vertical part that defines sidewalls of the field recess, and
wherein the horizontal part of the field liner layer contacts the lower insulating layer, and the vertical part of the field liner layer contacts the fin-shaped insulating layer.
5. The semiconductor device of claim 1 , wherein an upper surface of the field insulating layer is convex with respect to the upper surface of the lower insulating layer.
6. The semiconductor device of claim 1 , wherein the fin- shaped insulating layer comprises a first fin-shaped insulating layer,
wherein the semiconductor device further comprises a second fin-shaped insulating layer adjacent to the first fin-shaped insulating layer in the second direction, and
wherein at least a part of the second fin-shaped insulating layer overlaps the gate structures in the first direction.
7. The semiconductor device of claim 1 ,
wherein the lower insulating layer and the fin-shaped insulating layer comprise a same oxide-based insulating material,
wherein the source/drain region and the active pattern each comprise a semiconductor material,
wherein a bottom surface of the source/drain region contacts a first portion of the upper surface of the fin-shaped insulating layer,
wherein a second portion of the upper surface of the fin-shaped insulating layer contacts a bottom surface of another source/drain region, and
wherein a third portion of the upper surface of the fin-shaped insulating layer contacts a bottom surface of a first gate structure of the plurality of gate structures that is between the source/drain region and the other source/drain region.
8. The semiconductor device of claim 1 , wherein the active pattern comprises a first active pattern of a plurality of active patterns that are spaced apart from each other in a third direction intersecting the first direction and the second direction, and
wherein the fin-shaped insulating layer vertically protrudes upward beyond the upper surface of the lower insulating layer in the third direction.
9. The semiconductor device of claim 1 , wherein the active pattern does not directly contact the fin-shaped insulating layer, and
wherein the fin-shaped insulating layer directly contacts the lower insulating layer.
10. The semiconductor device of claim 1 , wherein the source/drain region comprises a first source/drain region, and the fin-shaped insulating layer comprises a first fin-shaped insulating layer,
wherein the semiconductor device further comprises:
a second source/drain region adjacent to the first source/drain region in the second direction; and
a second fin-shaped insulating layer adjacent to the first fin-shaped insulating layer in the second direction, and
wherein the second source/drain region does not overlap the second fin-shaped insulating layer in the first direction.
11. The semiconductor device of claim 1 , wherein an upper surface of the field insulating layer is lower than the upper surface of the fin-shaped insulating layer, with the upper surface of the lower insulating layer providing the base reference plane.
12. A semiconductor device comprising:
an insulating layer;
a trench that is in the insulating layer and extends in a first direction;
a field insulating layer that is in the trench;
a gate electrode that is on the insulating layer and extends in a second direction intersecting the first direction;
a source/drain region that is on the insulating layer beside the gate electrode; and
an active pattern that penetrates the gate electrode and is electrically connected to the source/drain region,
wherein the insulating layer comprises a first part overlapping the field insulating layer in a third direction intersecting the first direction and the second direction and a second part not overlapping the field insulating layer in the third direction,
wherein the second part of the insulating layer protrudes upward in the third direction beyond an upper surface of the first part of the insulating layer,
wherein a bottom surface of the source/drain region contacts the second part of the insulating layer, and
wherein the source/drain region does not overlap the second part of the insulating layer in the first direction.
13. The semiconductor device of claim 12 ,
wherein the field insulating layer comprises a field liner layer in the trench and a field filling layer that is on the field liner layer, and
wherein a sidewall of the second part of the insulating layer contacts the field liner layer.
14. The semiconductor device of claim 12 , wherein the insulating layer comprises an oxide-based insulating material, and
wherein the source/drain region and the active pattern each comprise a semiconductor material.
15. The semiconductor device of claim 12 , wherein the bottom surface of the source/drain region is coplanar with a bottom surface of the active pattern.
16. A semiconductor device comprising:
a lower insulating layer comprising a first region and a second region;
a first fin-shaped insulating layer on the first region of the lower insulating layer and vertically protruding from the first region of the lower insulating layer, the first fin-shaped insulating layer extending in a first direction;
a second fin-shaped insulating layer on the second region of the lower insulating layer and vertically protruding from the second region of the lower insulating layer, the second fin-shaped insulating layer extending in the first direction;
a plurality of gate structures that are on the first and second fin-shaped insulating layers and comprise a gate electrode intersecting the first and second fin-shaped insulating layers;
a first source/drain region that is on the first fin-shaped insulating layer,
a second source/drain region that is on the second fin-shaped insulating layer;
a first active pattern that is on the first fin-shaped insulating layer and penetrates the gate electrode and is electrically connected to the first source/drain region; and
a second active pattern that is on the second fin-shaped insulating layer and penetrates the gate electrode and is electrically connected to the second source/drain region,
wherein the gate electrode extends in a second direction intersecting the first direction,
wherein a bottom surface of the first source/drain region is higher than a bottom surface of the second source/drain region relative to an upper surface of the lower insulating layer, and
wherein the first source/drain region does not overlap the first fin-shaped insulating layer in the first direction, and at least a part of the second source/drain region overlaps the second fin- shaped insulating layer in the first direction.
17. The semiconductor device of claim 16 , wherein a height of the first fin-shaped insulating layer is greater than a height of the second fin-shaped insulating layer.
18. The semiconductor device of claim 16 , wherein the second source/drain region comprises silicon germanium (SiGe).
19. The semiconductor device of claim 16 , wherein the first source/drain region includes a different material from the second source/drain region.
20. The semiconductor device of claim 16 , wherein the bottom surface of the first source/drain region is coplanar with a bottom surface of at least one of the gate structures.