Semiconductor devices having improved electrical characteristics and methods of fabricating the same
The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.
1. A method of fabricating a semiconductor device, the method comprising:
forming, on a substrate, a device isolation layer that defines a plurality of active regions;
forming a plurality of word lines on the substrate;
forming a first contact hole by etching a portion of the substrate;
forming a contact pattern and a conductive layer on the contact pattern, wherein the contact pattern is within the first contact hole;
forming a plurality of bit-line structures by etching the contact pattern and the conductive layer;
forming a second contact hole by etching the active regions between the bit-line structures;
forming a first buried contact in a lower portion of the second contact hole;
forming a plurality of spacer structures that cover sidewalls of the bit-line structures; and
forming a second buried contact between the spacer structures,
wherein the forming of the spacer structures comprises:
forming a first spacer that covers each of the sidewalls of the bit-line structures;
forming a second spacer that covers a sidewall of the first spacer; and
forming a third spacer that covers a sidewall of the second spacer, and
wherein the second spacer is in contact with a portion of an outer wall of the device isolation layer.
2. The method of claim 1 , wherein the second spacer extends from the sidewall of the first spacer to the outer wall of the device isolation layer.
3. The method of claim 1 , further comprising forming a buffer pattern, wherein the forming of the buffer pattern comprises:
forming a buffer layer on the active regions and the device isolation layer, and
patterning the buffer layer.
4. The method of claim 3 , wherein the second spacer extends from the sidewall of the first spacer to a sidewall of the buffer pattern.
5. The method of claim 3 , wherein the forming of the first spacer comprises:
forming a first spacer layer covering the sidewalls of the bit-line structures and a top surface of the buffer layer; and
etching a portion of the first spacer layer.
6. The method of claim 1 , wherein the first buried contact is in contact with each of top surfaces of the active regions.
7. The method of claim 1 , wherein the forming of the second contact hole comprises etching the device isolation layer that surrounds the active regions between the bit-line structures.
8. The method of claim 1 , wherein the forming of the second spacer and the third spacer comprises:
forming a second spacer layer and a third spacer layer on the sidewall of the first spacer and a top surface of the first buried contact; and
etching a portion of the second spacer layer and a portion of the third spacer layer.
9. The method of claim 1 , wherein the second spacer is interposed between the first spacer and the third spacer.
10. A method of fabricating a semiconductor device, the method comprising:
forming, on a substrate, a device isolation layer that defines a plurality of active regions;
forming a plurality of word lines on the substrate;
forming a first contact hole by etching a portion of the substrate;
forming a contact pattern and a conductive layer on the contact pattern, wherein the contact pattern is within the first contact hole;
forming a plurality of bit-line structures by etching the contact pattern and the conductive layer;
forming a second contact hole by etching the active regions between the bit-line structures;
forming a first buried contact in a lower portion of the second contact hole;
forming a plurality of spacer structures that cover sidewalls of the bit-line structures; and
forming a second buried contact between the spacer structures,
wherein the forming of the spacer structures comprises:
forming a first spacer covering each of the sidewalls of the bit-line structures;
forming a second spacer covering a sidewall of the first spacer; and
forming a third spacer covering a sidewall of the second spacer, and
wherein the second spacer is in contact with a top surface of the first buried contact.
11. The method of claim 10 , wherein the forming of the spacer structures comprises enlarging the second contact hole by etching a portion of the first buried contact.
12. The method of claim 10 , wherein the second spacer includes a lower portion on the top surface of the first buried contact, and an upper portion vertically extending from the lower portion.
13. The method of claim 12 , wherein the third spacer is provided on a top surface of the lower portion and a sidewall of the upper portion.
14. The method of claim 12 , wherein the third spacer is spaced apart from the first buried contact with the lower portion of the second spacer interposed therebetween.
15. The method of claim 10 , wherein the top surface of the first buried contact comprises a first surface being in contact with the second spacer and a second surface being in contact with the second buried contact, and
wherein the first surface is a flat surface and the second surface is a concave surface.
16. A method of fabricating a semiconductor device, the method comprising:
forming, on a substrate, a device isolation layer that defines a plurality of active regions;
forming a plurality of word lines on the substrate;
forming a first contact hole by etching a portion of the substrate;
forming a contact pattern and a conductive layer on the contact pattern, wherein the contact pattern is within the first contact hole;
forming a plurality of bit-line structures by etching the contact pattern and the conductive layer;
forming a second contact hole by etching the active regions between the bit-line structures;
forming a first buried contact in a lower portion of the second contact hole;
forming a plurality of spacer structures that cover sidewalls of the bit-line structures; and
forming a second buried contact between the spacer structures,
wherein the forming of the spacer structures comprises:
forming a first spacer covering each of the sidewalls of the bit-line structures;
forming a second spacer covering a sidewall of the first spacer; and
forming a third spacer covering a sidewall of the second spacer, and
wherein a top surface of the third spacer is located at a lower level than a top surface of the first spacer and a top surface of the second spacer.
17. The method of claim 16 , further comprising forming a dielectric pattern on the third spacer.
18. The method of claim 17 , wherein the forming of the dielectric pattern comprises:
forming a dielectric layer on a portion of the sidewall of the second spacer, the top surface of the third spacer, and a top surface of the second buried contact, and
patterning the dielectric layer.
19. The method of claim 17 , wherein a sidewall of the dielectric pattern is spaced apart from a sidewall of the third spacer.
20. The method of claim 16 , wherein the third spacer is spaced apart from the first buried contact with the second spacer interposed therebetween.