Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

1. A method comprising:

adjusting a step of a duty cycle adjuster of a memory by a first step size responsive to a first value of a duty cycle code written to a mode register of the memory, wherein the first value is based, at least in part, on a result of a first duty cycle monitor sequence; and

adjusting the step of the duty cycle adjuster by a second step size responsive to a second value of the duty cycle code written to the mode register, wherein the second step size is smaller than the first step size, wherein the second value is based, at least in part, on a result of a second duty cycle monitor sequence.

2. The method of claim 1 , further comprising:

performing the first duty cycle monitor sequence; and

performing the second duty cycle monitor sequence.

3. The method of claim 2 , wherein the first duty cycle monitor sequence, the second duty cycle monitor sequence, or both, are performed responsive to a mode register write command received from a memory controller.

4. The method of claim 2 , further comprising:

exiting the first duty cycle monitor sequence; and

exiting the second duty cycle monitor sequence.

5. The method of claim 4 , where the first duty cycle monitor sequence, the second duty cycle monitor sequence, or both, are exited responsive to a mode register write command received from a memory controller.

6. The method of claim 2 , further comprising:

writing the result of the first duty cycle monitor sequence to the mode register; and

writing the result of the second duty cycle monitor sequence to the mode register.

7. The method of claim 6 , further comprising providing the result of the first duty cycle monitor sequence or the second duty cycle monitor sequence responsive to a mode register read command received from a memory controller.

8. The method of claim 1 , wherein the first step size comprises a step size of two steps of a duty cycle adjuster range and wherein the second step size comprises a step size of one step of the duty cycle adjuster range.

9. A method, comprising:

adjusting, with a duty cycle adjuster of a memory, a duty cycle of an internal clock of the memory according to a fast speed adjustment by writing a duty cycle code to a mode register of the memory; and

adjusting the duty cycle of the internal clock according to a slow speed adjustment.

10. The method of claim 9 wherein the fast speed adjustment comprises adjusting the duty cycle code of the duty cycle adjuster by a first step size and wherein the slow speed adjustment comprises adjusting the duty cycle code of the duty cycle adjuster by a second step size that is less steps than the first step size.

11. The method of claim 9 , further comprising performing a plurality of duty cycle monitor sequences prior to adjusting the duty cycle according to the fast speed adjustment and the slow speed adjustment.

12. The method of claim 11 , further comprising providing the duty cycle results for each of the plurality of duty cycle monitor sequences from the mode register responsive to a mode register read command received from a memory controller.

13. The method of claim 11 , wherein the duty cycle results include results for a first input condition and a second input condition for a duty cycle monitor of the memory, wherein the first and second input conditions are flipped.

14. The method of claim 9 , further comprising determining to switch from the fast speed adjustment to the slow speed adjustment based on a change from a first duty cycle condition to a second duty cycle condition that is opposite of the first duty cycle condition.

15. A method, comprising:

performing, with a duty cycle monitor of a memory, a plurality of duty cycle monitor sequences;

changing a duty cycle code for a duty cycle adjuster of the memory by writing the duty cycle code in a mode register of the memory following each of the plurality of duty cycle monitor sequences, wherein the duty cycle code is changed using at least two different amounts of adjustment for the plurality of duty cycle monitor sequences; and

writing duty cycle results from each of the plurality of duty cycle monitor sequences to the mode register.

16. The method of claim 15 wherein performing the plurality of duty cycle monitor are performed responsive to receiving at least one mode register write command from a mode register write command.

17. The method of claim 15 further comprising switching inputs of the duty cycle monitor of the memory during each of the plurality of duty cycle monitor sequences.

18. The method of claim 15 further comprising exiting each of the duty cycle monitor sequences responsive to a mode register write command received from a memory controller.

19. The method of claim 15 wherein changing the duty cycle code for the duty cycle adjuster is performed responsive to receiving a mode register write command and a new value for the duty cycle code from a memory controller.

20. The method of claim 19 wherein the value for the duty cycle code of a duty cycle monitor sequence is changed based on the duty cycle results from the duty cycle monitor sequence.