Memory device and method of operating the same

1. A memory device, comprising:

a plurality of memory cells including a first memory cell and a second memory cell, wherein the first and second memory cells share a first word line transistor;

a first bit line connected to the first memory cell;

a second bit line connected to the second memory cell;

a first word line connected to the first word line transistor shared by the first and second memory cells;

a first control transistor connected to the first bit line;

a second control transistor connected to second bit line;

a first mux transistor commonly connected to the first and second control transistors; and

a sense amplifier connected to the first mux transistor.

2. The memory device of claim 1 , wherein the first and second control transistors each has a gate terminal connected to a common gate control line.

3. The memory device of claim 2 , further comprising a controller, during a read operation of the first memory cell connected to the first word line, configured to:

activate the first word line;

activate the common gate control line; and

activate a mux control line connected to a gate terminal of the first mux transistor.

4. The memory device of claim 3 , further comprising a third control transistor connected to the first and second control transistors and ground.

5. The memory device of claim 4 , wherein the controller, during the read operation, is further configured to deactivate a control line connected to a gate terminal of the third control transistor.

6. The memory device of claim 5 , further comprising a second word line connected to third and fourth memory cells of the plurality of memory cells.

7. The memory device of claim 6 , wherein the controller is configured to, during the read operation, deactivate the second word line.

8. The memory device of claim 1 , wherein the plurality of memory cells each comprise a storage unit including a resistor or a capacitor.

9. The memory device of claim 1 , wherein the first word line is connected to an M number of the plurality of memory cells, and the sense amplifier is connected to an N number of mux transistors including the first mux transistor, where M and N are positive integers.

10. The memory device of claim 9 , wherein a number of a plurality of control transistors, including the first and second control transistors, connected to a common gate line and a plurality of bit lines, including the first and second bit lines, connected to the mux transistor are equal to M.

11. A method of operating a memory device, comprising:

activating, during a read operation of a first memory cell, a first word line connected to a first word line transistor shared by the first memory cell and a second memory cell;

activating a first control gate line connected to the first memory cell;

activating a mux control line connected to a mux transistor, the mux transistor connected to a sense amplifier; and

activating a common gate signal line connected to a gate terminal of a first common gate transistor connected to the first memory cell and a gate terminal of a second common gate transistor connected to the second memory cell.

12. The method of claim 11 , further comprising deactivating a second word line connected to a second word line transistor shared by a third memory cell and a fourth memory cell, wherein the second word line transistor having has (i) a drain terminal connected to a first control gate transistor of the third memory cell and a second control gate transistor of the fourth memory cell and Iii) a source terminal connected to the ground.

13. The method of claim 11 , further comprising deactivating a second control gate line connected to the second memory cell.

14. The method of claim 11 , wherein the memory cell includes a storage unit including a resistor or a capacitor.

15. The method of claim 11 , wherein the first and second common gate transistors, the mux transistor, and a control transistor are connected to one another at a node.

16. A memory system, comprising:

a plurality of memory cells including a first memory cell and a second memory cell, wherein the first and second memory cells share a first word line transistor;

a sense amplifier connected to the plurality of memory cells via a plurality of bit lines; and

a controller connected to the plurality of memory cells, wherein the controller is configured to:

activate, during a read operation of a first memory cell, a first word line connected to the first word line transistor shared by the first memory cell and a second memory cell;

activate a first control gate line connected to the first memory cell;

activate a mux control line connected to a mux transistor, the mux transistor connected to a sense amplifier; and

activate a common gate signal line connected to a gate terminal of a first common gate transistor connected to the first memory cell and a gate terminal of a second common gate transistor connected to the second memory cell.

17. The memory system of claim 16 , wherein the controller is further configured to deactivate a second word line connected to a second word line transistor shared by a third memory cell and a fourth memory cell, wherein the second word line transistor has (i) a drain terminal connected to the first control gate transistor of the third memory cell and a second control gate transistor of the fourth memory cell and cii) a source terminal connected to the ground.

18. The memory system of claim 16 , wherein the controller is further configured to deactivate a second control gate line connected to the second memory cell.

19. The memory system of claim 16 , wherein the plurality of memory cells each include a storage unit including a resistor or a capacitor.

20. The memory system of claim 16 , wherein the first and second common gate transistors, the mux transistor, and a control transistor are connected to one another at a node.