CYBER SECURITY AND TAMPER DETECTION TECHNIQUES WITH A DISTRIBUTED PROCESSOR MEMORY CHIP
In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.
1 . An integrated circuit, comprising:
a substrate;
a memory array disposed on the substrate, the memory array including a plurality of discrete memory banks;
a processing array disposed on the substrate, the processing array including a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks; and
a controller configured to:
implement at least one security measure with respect to an operation of the integrated circuit.
2 . The integrated circuit of claim 1 , wherein the controller is configured to take one or more remedial actions if the at least one security measure is triggered.
3 . The integrated circuit of claim 1 , wherein the controller is configured to implement at least one security measure in at least one memory location.
4 . (canceled)
5 . The integrated circuit of claim 1 , wherein the controller is configured to implement at least one security measure that includes locking access to one or more memory portions of the memory array not used for input data or output data operations.
6 . The integrated circuit of claim 1 , wherein the controller is configured to implement at least one security measure that includes locking only a subset of the memory array.
7 . The integrated circuit of claim 6 , wherein the subset of the memory array is designated by certain memory addresses.
8 . The integrated circuit of claim 6 , wherein the subset of the memory array is configurable.
9 . The integrated circuit of claim 1 , wherein the controller is configured to implement at least one security measure that includes controlling traffic to or from the integrated circuit.
10 . The integrated circuit of claim 1 , wherein the controller is configured to implement at least one security measure that includes uploading a changeable data, code, or fixed data.
11 . The integrated circuit of claim 10 , wherein the uploading of the changeable data, code, or fixed data occurs during a boot process.
12 . The integrated circuit of claim 1 , wherein the controller is configured to implement at least one security measure that includes, during a boot process, uploading a configuration file that identifies certain memory addresses for at least part of the memory array to be locked upon completion of the boot process.
13 . The integrated circuit of claim 1 , wherein the controller is further configured to require a passphrase to unlock access to a memory portion of the memory array associated with one or more memory addresses.
14 . The integrated circuit of claim 1 , wherein the at least one security measure is triggered upon detection of an attempted access to at least one locked memory address.
15 . The integrated circuit of claim 1 , wherein the controller is configured to implement at least one security measure that includes:
calculating a checksum, a hash, CRC (cyclic redundancy check), or parity calculated with respect to at least portion of the memory array; and
comparing the calculated checksum, hash, CRC, or parity with a predetermined value.
16 . (canceled)
17 . The integrated circuit of claim 1 , wherein the at least one security measure includes duplicating a program code in at least two different memory portions.
18 - 20 . (canceled)
21 . The integrated circuit of claim 1 , wherein the at least one security measure includes determining whether an operation pattern is different from one or more predetermined operation patterns.
22 . The integrated circuit of claim 2 , wherein the one or more remedial actions include halting execution of operation.
23 . A method of securing an integrated circuit against tampering, the method including:
implementing, using a controller associated with the integrated circuit, at least one security measure with respect to an operation of the integrated circuit;
wherein the integrated circuit includes:
a substrate;
a memory array disposed on the substrate, the memory array including a plurality of discrete memory banks; and
a processing array disposed on the substrate, the processing array including a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks.
24 . The method of claim 23 , further including taking one or more remedial actions if the at least one security measure is triggered.
25 . An integrated circuit, comprising:
a substrate;
a memory array disposed on the substrate, the memory array including a plurality of discrete memory banks;
a processing array disposed on the substrate, the processing array including a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks; and
a controller configured to:
implement at least one security measure with respect to an operation of the integrated circuit; wherein the at least one security measure includes duplicating a program code in at least two different memory portions.
26 - 368 . (canceled)