In-memory zero value detection
In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.
1. A memory unit comprising:
a memory array including a plurality of memory banks;
at least one controller configured to control at least one aspect of read operations relative to the plurality of memory banks;
at least one multi-bit zero value detection logic unit configured to detect a multi-bit zero value associated with data and prevent retrieval of the data, wherein the data is stored in a particular address of the plurality of memory banks;
at least one read-disable element configured to interrupt a read command associated with the particular address when the at least one multi-bit zero value detection logic unit detects the multi-bit zero value associated with the particular address; and
wherein the at least one controller is configured to return a multi-bit zero value indicator to one or more circuits in response to a multi-bit zero value detection by the at least one multi-bit zero value detection logic unit.
2. The memory unit of claim 1 , wherein the one or more circuits to which the multi-bit zero value indicator is returned are outside the memory unit.
3. The memory unit of claim 1 , wherein the one or more circuits to which the multi-bit zero value indicator is returned are inside the memory unit.
4. The memory unit of claim 1 , wherein the at least one controller is configured to send the multi-bit zero value indicator to the one or more circuits instead of sending the data stored in the particular address.
5. The memory unit of claim 1 , wherein a size of the multi-bit zero value indicator is smaller than a size of the data.
6. The memory unit of claim 1 , wherein an energy consumed by a first process that comprises (a) detecting the multi-bit zero value, (b) generating the multi-bit zero value indicator, and (c) sending the multi-bit zero value indicator to the one or more circuits is smaller than an energy consumed by sending the data to the one or more circuits.
7. The memory unit of claim 1 , wherein the memory unit further includes at least one sense amplifier configured to preclude activation of at least one of the plurality of memory banks after a zero value detection by the at least one multi-bit zero value detection logic unit.
8. The memory unit of claim 1 , wherein each of the plurality of memory banks is further organized into sub-banks, the at least one controller includes a sub-bank controller, and wherein the at least one multi-bit zero value detection logic unit includes a zero value detection logic associated with the sub-banks.
9. The memory unit of claim 1 , further including a plurality of processor subunits spatially distributed within the memory unit, wherein each of the plurality of processor subunits is operably connected with a corresponding at least one of the plurality of memory banks, and wherein each of the plurality of processor subunits is configured to access and operate on data stored in the corresponding at least one memory bank.
10. The memory unit of claim 1 , further comprising:
a processing unit configured to:
send read requests to the memory banks;
receive the zero value indicator; and
based on the received zero value indicator, forego transfer of the multi-bit zero value.
11. The memory unit of claim 1 , wherein:
the at least one controller is further configured to control at least one aspect of write operations relative to the plurality of memory banks;
the at least one multi-bit zero value detection logic unit is further configured to detect a user-adjusted value associated with data to be written to an address of the plurality of memory banks; and
the at least one controller is further configured to provide a value indicator to the one or more circuits in response to a detection by the at least one multi-bit zero value detection logic unit of the user-adjusted value.
12. A method for detecting a zero value in a particular address of a plurality of memory banks of a memory unit, comprising:
receiving, from a circuit outside the memory unit, a request to read data stored in the particular address of the plurality of memory banks of the memory unit;
activating, by a controller, in response to the received request, a zero value detection logic unit to detect the zero value in the particular address and prevent retrieval of the data;
transmitting, by the controller, in response to the zero value detection by the zero value detection logic unit, a zero value indicator to the circuit; and
configuring, by the controller, a read-disable element to interrupt a read command associated with the particular address when the zero value detection logic unit detects the zero value associated with the particular address.
13. The method of claim 12 , further comprising configuring, by the controller, a sense amplifier to preclude an activation of at least one of the plurality of memory banks when the zero value detection logic unit detects the zero value.
14. A non-transitory computer-readable medium storing a set of instructions that are executable by a controller of a memory unit to perform operations to cause the memory unit to detect a zero value in a particular address of a plurality of memory banks of a memory unit, the operations comprising:
receiving, from a circuit outside the memory unit, a request to read data stored in the particular address of the plurality of memory banks of the memory unit;
activating, by a controller, in response to the received request, a zero value detection logic unit to detect the zero value in the particular address by a controller and prevent retrieval of the data;
transmitting, by the controller, in response to the zero value detection by the zero value detection logic unit, a zero value indicator to the circuit; and
configuring, by the controller, a read-disable element to interrupt a read command associated with the particular address when the zero value detection logic unit detects the zero value associated with the particular address.
15. The non-transitory computer-readable medium of claim 14 , wherein the operations further comprise configuring, by the controller, a sense amplifier to preclude an activation of at least one of the plurality of memory banks when the zero value logic detection unit detects the zero value.