Transient stabilized SOI FETs
Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both V GS and V DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.
1. An integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) high resistivity substrate, including at least one field effect transistor (FET) having a V GS characteristic and configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V GS characteristic as during an active mode, thereby eliminating or reducing changes in accumulated charge, further including at least one substrate contact near at least one FET, each substrate contact comprising a resistive conduction path formed between a first contact region at a surface of a layer of the integrated circuit and a second contact region at or near a surface of the high resistivity substrate, wherein each substrate contact penetrates through at least one dielectric layer.
2. The invention of claim 1 , wherein the SOI substrate includes a trap rich layer susceptible to accumulated charge in or near such trap rich layer and each substrate contact penetrates into the trap rich layer.
3. The invention of claim 1 , further including at least a partial ring of substrate contacts around at least one FET.
4. A circuit fabricated on a high resistivity silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit including, the circuit including:
(a) at least one field effect transistor (FET) having a drain, a source, a gate, a V GS characteristic, and a signal path through the FET between the drain and the source;
(b) a switch coupled to the signal path of the FET, configured to selectively couple the signal path to a load or interrupt current flow through the signal path of the FET; and
(c) at least one substrate contact near at least one FET, each substrate contact comprising a resistive conduction path formed between a first contact region at a surface of a layer of the integrated circuit and a second contact region at or near a surface of the high resistivity SOI substrate, wherein each substrate contact penetrates through at least one dielectric layer;
wherein, in an active mode, the switch couples the signal path of the FET to the load; and
wherein, in a standby mode, the switch interrupts current flow through the signal path of the FET, thereby maintaining essentially the same V GS characteristic as during the active mode, and thereby eliminating or reducing changes in accumulated charge.
5. The invention of claim 4 , wherein the SOI substrate includes a trap rich layer susceptible to accumulated charge in or near such trap rich layer and each substrate contact penetrates into the trap rich layer.
6. The invention of claim 4 , further including at least a partial ring of substrate contacts around at least one FET.
7. A circuit fabricated on a high resistivity silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit including:
(a) at least one field effect transistor (FET) having a drain, a source, a gate, a V DS characteristic, a V GS characteristic, and a signal path through the FET between the drain and the source; and
(b) a switch coupled to the signal path of the FET, configured to selectively couple the signal path to a first current source or to a second current source, the second current source providing a lower current than the first current source; and
(c) at least one substrate contact near at least one FET, each substrate contact comprising a resistive conduction path formed between a first contact region at a surface of a layer of the integrated circuit and a second contact region at or near a surface of the high resistivity SOI substrate, wherein each substrate contact penetrates through at least one dielectric layer;
wherein, in an active mode, the switch couples the signal path of the FET to the first current source; and
wherein, in a standby mode, the switch couples the signal path of the FET to the second current source, such that both the V GS characteristic and the V DS characteristic of the FET are close to respective active mode operational voltages for the V GS characteristic and the V DS characteristic, thereby reducing changes in accumulated charge.
8. The invention of claim 7 , wherein the SOI substrate includes a trap rich layer susceptible to accumulated charge in or near such trap rich layer and each substrate contact penetrates into the trap rich layer.
9. The invention of claim 7 , further including at least a partial ring of substrate contacts around at least one FET.