IP Library › Granted Patent US 12,279,424
Granted Patent B2
US 12,279,424 · App. 17/670,999 · Granted Apr 15, 2025

Semiconductor device and manufacturing method of semiconductor device

Inventors: Yu Nakane (Kawasaki Kanagawa, JP); Nobuyuki Toda (Kawasaki Kanagawa, JP); Hiroyoshi Kitahara (Yokohama Kanagawa, JP); Takeshi Yamamoto (Kawasaki Kanagawa, JP); Naozumi Terada (Kawasaki Kanagawa, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H10B41/30H01L29/66825H01L29/66833H01L29/788H01L29/792H10B43/30
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Quick Facts
Patent No.
US 12,279,424
App. No.
17/670,999
Granted
Apr 15, 2025
Kind
B2
Abstract

According to the present embodiment, a semiconductor device includes a semiconductor substrate, a memory transistor, and a MOS transistor. The memory transistor includes at least a first silicon dioxide film and a first gate electrode positioned on the semiconductor substrate in order. The MOS transistor includes a second silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order. Any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the memory transistor.

Claims (19)

1. A semiconductor device comprising:

a semiconductor substrate;

a charge trap memory transistor comprising at least a first silicon dioxide film, a first silicon nitride film, a second silicon dioxide film, and a first gate electrode positioned on the semiconductor substrate in order, and a third silicon dioxide film formed around side surfaces of the second silicon dioxide film and side surfaces of the first gate electrode; and

a MOS transistor comprising a fourth silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order, wherein

a thickness of the third silicon dioxide film is 1 to 0.778 (˜35/45) times a thickness of the fourth silicon dioxide film, and any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the charge trap memory transistor.

2. The device of claim 1 , wherein the fourth silicon dioxide film is formed after the first gate electrode is formed.

3. The device of claim 1 , wherein the third silicon dioxide film is also formed around side surfaces of the first silicon nitride film.

4. A semiconductor device comprising:

a semiconductor substrate;

a floating gate memory transistor comprising at least a first silicon dioxide film, a first silicon nitride film, a floating gate electrode, a second silicon dioxide film, and a first gate electrode positioned on the semiconductor substrate in order, and a third silicon dioxide film formed around side surfaces of the floating gate electrode and side surfaces of the first gate electrode; and

a MOS transistor comprising a fourth silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order, wherein

a thickness of the third silicon dioxide film is 1 to 0.778 (˜35/45) times a thickness of the fourth silicon dioxide film, and any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the floating gate memory transistor.

5. The device of claim 1 , wherein the bird's beak is a region where oxidation has gradually progressed, and the bird's beak is not generated in at least either the second silicon dioxide film or the first gate electrode in a process of generating the fourth silicon dioxide film.

6. The device of claim 4 , wherein a width of the floating gate electrode is equal to or less than a width of the first gate electrode.

7. A semiconductor device comprising:

a semiconductor substrate;

a memory transistor comprising at least a first silicon dioxide film and a first gate electrode positioned on the semiconductor substrate in order, and a second silicon dioxide film formed around side surfaces of the first gate electrode; and

a MOS transistor comprising a third silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order, wherein

a thickness of the second silicon dioxide film is 1 to 0.778 (˜35/45) times a thickness of the third silicon dioxide film, and any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the memory transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2022
From: NAKANE, YU; TODA, NOBUYUKI; KITAHARA, HIROYOSHI; YAMAMOTO, TAKESHI; TERADA, NAOZUMI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 059004/0415 →
Priority Claims (2)
JP 2021-152203 · Sep 17, 2021 · national
JP 2021-200121 · Dec 9, 2021 · national
Continuity (1)
Related Publication 20230090702A1 · Mar 23, 2023
References Cited (17)
US 5953611A · Tanaka · 1999 [cited by applicant]
US 10651188B2 · Yamakoshi et al. · 2020 [cited by applicant]
US 20020149046A1 · Takahashi · 2002 [cited by examiner]
US 20040166643A1 · Doan · 2004 [cited by examiner]
US 20070196982A1 · Eitan · 2007 [cited by examiner]
US 20080087943A1 · Kajimoto · 2008 [cited by examiner]
US 20140159122A1 · Sato · 2014 [cited by examiner]
US 20140264554A1 · Lim · 2014 [cited by examiner]
US 20160163722A1 · Chang · 2016 [cited by examiner]
US 20180286881A1 · Yamakoshi · 2018 [cited by examiner]
US 20200286915A1 · Cui · 2020 [cited by examiner]
JP H09321255A · 1997 [cited by applicant]
JP 2016146508A · 2016 [cited by examiner]
JP 2018170444A · 2018 [cited by applicant]
Nathan Cheung, “Thermal Oxidation of Si”, EE143 Lecture #5, U.C. Berkeley, 2013, 22 pages. [cited by applicant]
Non-Final Office Action mailed Mar. 28, 2024 in corresponding U.S. Appl. No. 18/366,353, 15 pages. [cited by applicant]
Notice of Reasons for Refusal (Office Action) mailed Jan. 17, 2025 in Japanese Patent Application No. 2021-200121 with English machine translation, 18 pages. [cited by applicant]