Memory devices and methods of manufacturing thereof
View Patent ↗A semiconductor device includes a first and a second areas. The first area includes a plurality of first conductive stripes extending along a lateral direction and spaced from one another along a vertical direction, a first memory layer extending along the vertical direction, a first semiconductor layer extending along the vertical direction and coupled to a portion of the first memory layer, and second and third conductive stripes extending along the vertical direction, wherein the second and third conductive stripes are coupled to end portions of a sidewall of the first semiconductor layer. The second area includes a plurality of conductive sheets extending along the lateral direction and spaced from one another along the vertical direction, a second memory layer extending along the vertical direction and wrapped by the plurality of conductive sheets, and a second semiconductor layer extending along the vertical direction and wrapped by the second memory layer.
1 . A memory device, comprising:
a substrate including a first area and a second area;
wherein the memory device, in the first area, comprises:
a plurality of first conductive stripes extending along a lateral direction and spaced from one another along a vertical direction;
a first memory layer extending along the vertical direction;
a first semiconductor layer extending along the vertical direction and coupled to a portion of the first memory layer; and
second and third conductive stripes extending along the vertical direction, wherein the second and third conductive stripes are coupled to end portions of a sidewall of the first semiconductor layer; and
wherein the memory device, in the second area, comprises:
a plurality of conductive sheets extending along the lateral direction and spaced from one another along the vertical direction;
a second memory layer extending along the vertical direction and wrapped by the plurality of conductive sheets; and
a second semiconductor layer extending along the vertical direction and wrapped by the second memory layer.
2 . The memory device of claim 1 , wherein the first area is located immediately next to the second area.
3 . The memory device of claim 1 , wherein the second memory layer continuously extends along the vertical direction, with a plurality of portions discretely wrapped by the plurality of conductive sheets, respectively.
4 . The memory device of claim 1 , wherein the second semiconductor layer continuously extends along the vertical direction, with a plurality of portions discretely wrapped by the plurality of conductive sheets, respectively.
5 . The memory device of claim 1 , wherein the plurality of first conductive stripes, the first memory layer, the first semiconductor layer, and the second and third conductive stripes collectively function as a portion of an active memory array, while the plurality of conductive sheets, the second memory layer, and the second semiconductor layer collectively function as a portion of a dummy memory array.
6 . The memory device of claim 1 , wherein the memory device, in the second area, further comprises:
a pair of fourth conductive stripes extending along the vertical direction;
wherein the second semiconductor layer wraps the pair of fourth conductive stripes and a single dielectric pillar interposed between the pair of fourth conductive stripes.
7 . The memory device of claim 1 , wherein the memory device, in the second area, further comprises:
a single fifth conductive structure extending along the vertical direction;
wherein the second semiconductor layer wraps the fifth conductive structure and a pair of dielectric pillars disposed on opposite sides of the single fifth conductive structure, respectively.
8 . The memory device of claim 1 , wherein the memory device, in the second area, further comprises:
a single sixth conductive structure extending along the vertical direction;
wherein the second semiconductor layer wraps the sixth conductive structure and a single dielectric pillar disposed on a side of the sixth conductive structure.
9 . The memory device of claim 1 , further comprises:
a dielectric pillar extending along the vertical direction;
wherein the second semiconductor layer wraps the dielectric pillar, with no conductive material disposed between the dielectric pillar and the second semiconductor layer.
10 . The memory device of claim 1 , further comprises:
a single seventh conductive structure extending along the vertical direction;
wherein the second semiconductor layer wraps the single seventh conductive structure, with no dielectric material disposed between the single seventh conductive structure and the second semiconductor layer.
11 . The memory device of claim 10 , wherein the single seventh conductive structure has a cross-section with a rectangular shape, a square shape, a circular shape, or an elliptical shape.
12 . A memory device, comprising:
a plurality of active memory arrays disposed over a substrate; and
a plurality of dummy memory arrays disposed over the substrate, wherein each of the plurality of active memory arrays is interposed between a pair of the plurality of dummy memory arrays along a first lateral direction;
wherein each of the plurality of active memory arrays comprises a plurality of first memory layers extending along a vertical direction and a plurality of first semiconductor layers extending along the vertical direction; and
wherein each of the plurality of dummy memory arrays comprises a plurality of second memory layers extending along the vertical direction and a plurality of second semiconductor layers extending along the vertical direction.
13 . The memory device of claim 12 , wherein one of the plurality of first semiconductor layers extends along a portion of a sidewall of a corresponding one of the plurality of first memory layers.
14 . The memory device of claim 12 , wherein one of the plurality of second memory layers wraps around a corresponding one of the plurality of second semiconductor layers.
15 . The memory device of claim 14 , wherein each of the plurality of second semiconductor layers surrounds at least one of: a conductive structure extending along the vertical direction or a dielectric pillar extending along the vertical direction.
16 . The memory device of claim 12 , wherein each of the plurality of active memory arrays comprises a plurality of conductive stripes separated from one another along the vertical direction and extending along a second lateral direction perpendicular to the first lateral direction.
17 . The memory device of claim 15 , wherein each of the plurality of dummy memory arrays comprises a plurality of conductive sheets separated from one another along the vertical direction and extending along a second lateral direction perpendicular to the first lateral direction.
18 . A memory device, comprising:
a plurality of active memory arrays disposed over a substrate; and
a plurality of dummy memory arrays disposed over the substrate, wherein the plurality of active memory arrays and the plurality of dummy arrays are arranged in an alternating pattern along a first lateral direction;
wherein each of the plurality of active memory arrays comprises a plurality of first memory layers extending along a vertical direction and a plurality of first semiconductor layers extending along the vertical direction; and
wherein each of the plurality of dummy memory arrays comprises a plurality of second memory layers extending along the vertical direction and a plurality of second semiconductor layers extending along the vertical direction, each of the plurality of second semiconductor layers encloses each corresponding one of the second memory layers.
19 . The memory device of claim 18 , wherein each of the plurality of second semiconductor layers encloses a conductive structure extending along the vertical direction, a dielectric pillar extending along the vertical direction, or both.
20 . The memory device of claim 19 , wherein each of the plurality of second semiconductor layers encloses the conductive structure and the dielectric pillar, and wherein the dielectric pillar is interposed between portions of the conductive structure.