IP Library › Granted Patent US 12,402,374
Granted Patent B2
US 12,402,374 · App. 17/673,239 · Granted Aug 26, 2025

Electronic device including two-dimensional material and method of manufacturing the same

Inventors: Junyoung Kwon (Seoul, KR); Minsu Seol (Seoul, KR); Hyeonjin Shin (Suwon-si, KR); Minseok Yoo (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10D62/118H10D30/031H10D30/6713H10D30/6729H10D62/292H10D62/80H10D62/882H10D64/01
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Quick Facts
Patent No.
US 12,402,374
App. No.
17/673,239
Granted
Aug 26, 2025
Kind
B2
Abstract

An electronic device including a two-dimensional material is provided. The electronic device may include a substrate; a metal layer on a partial region of the substrate; a two-dimensional material layer over the metal layer and an upper surface of the substrate; and an insertion layer between the metal layer and the two-dimensional material layer.

Claims (63)

1. An electronic device comprising:

a substrate;

a metal layer on a partial region of the substrate;

a two-dimensional material layer over the metal layer and an upper surface of the substrate; and

an insertion layer between the metal layer and the two-dimensional material layer, wherein

the two-dimensional material layer directly contacts a first surface of the insertion layer,

a second surface of the insertion layer directly contacts the metal layer,

the second surface of the insertion layer is opposite the first surface of the insertion layer, and

the two-dimensional material layer extends over a region of the upper surface of the substrate that is not covered by the metal layer.

2. The electronic device of claim 1 ,

wherein the two-dimensional material layer comprises a transferable two-dimensional material.

3. The electronic device of claim 1 ,

wherein the two-dimensional material layer comprises at least one of graphene, black phosphorus, or transition metal dichalcogenide (TMD).

4. The electronic device of claim 1 ,

wherein the metal layer comprises a metal having a low work function or a noble metal.

5. The electronic device of claim 4 ,

wherein the insertion layer comprises graphene, a-C, h-BN, or a-BN.

6. The electronic device of claim 1 ,

wherein the insertion layer comprises graphene, a-C, h-BN, or a-BN.

7. The electronic device of claim 1 ,

wherein the metal layer has a step with respect to a reference surface, and

wherein the two-dimensional material layer comprises a first portion along the reference surface, a second portion on the metal layer; and

an inclined third portion between the first portion and the second portion.

8. The electronic device of claim 7 ,

wherein the two-dimensional material layer comprises a transferred two-dimensional material layer, and

wherein the inclined third portion corresponds to a suspended portion.

9. The electronic device of claim 7 , further comprising:

an upper metal layer on the two-dimensional material layer,

wherein the upper metal layer corresponds to the metal layer.

10. The electronic device of claim 1 , further comprising:

a planarization layer on the substrate, the planarization layer exposing an upper surface of the metal layer,

wherein the two-dimensional material layer extends over the metal layer and the planarization layer.

11. The electronic device of claim 10 , further comprising:

an upper metal layer on the two-dimensional material layer,

wherein the upper metal layer corresponds to the metal layer.

12. The electronic device of claim 1 ,

wherein the metal layer comprises a first electrode and a second electrode spaced apart from each other on an upper surface of the substrate,

wherein the two-dimensional material layer contacts an upper surface of the first electrode, two-dimensional material layer contacts an upper surface of the second electrode, and covers an upper surface of a part of the substrate between the first electrode and the second electrode,

the part of the substrate between the first electrode and the second electrode is the region of the substrate not covered by the metal layer.

13. The electronic device of claim 12 , further comprising:

a gate insulating layer on the two-dimensional layer; and

a gate electrode on the gate insulating layer, wherein

the two-dimensional material layer is a channel layer.

14. The electronic device of claim 13 ,

wherein the gate insulating layer comprises at least one of a high-k oxide, a silicon oxide, or a two-dimensional insulating material capable of atomic layer deposition (ALD).

15. An electronic device comprising:

a substrate;

a metal layer on a partial region of the substrate;

a two-dimensional material layer over the metal layer and an upper surface of the substrate; and

an insertion layer between the metal layer and the two-dimensional material layer,

wherein the metal layer comprises a first electrode and a second electrode spaced apart from each other on the substrate, and

wherein the two-dimensional material layer covers an upper surface of the first electrode, an upper surface of the second electrode, and an upper surface of a part of the substrate between the first electrode and the second electrode.

16. The electronic device of claim 15 , further comprising:

a gate insulating layer on the two-dimensional material layer; and

a gate electrode on the gate insulating layer, wherein

the two-dimensional material layer is a channel layer.

17. The electronic device of claim 16 ,

wherein the gate insulating layer comprises at least one of a high-k oxide, a silicon oxide, or a two-dimensional insulating material capable of atomic layer deposition (ALD).

18. The electronic device of claim 15 ,

the two-dimensional layer extends over a region of the upper surface of the substrate that is not covered by the metal layer,

the part of the substrate between the first electrode and the second electrode is the region of the substrate not covered by the metal layer,

the two-dimensional material layer contacts the upper surface of the first electrode, the two-dimensional dimensional material layer contacts the upper surface of the second electrode, and

the upper surface of the first electrode and the upper surface of the second electrode are parallel to each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2022
From: KWON, JUNYOUNG; SEOL, MINSU; SHIN, HYEONJIN; YOO, MINSEOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 059065/0082 →
Priority Claims (1)
KR 10-2021-0112472 · Aug 25, 2021 · national
Continuity (1)
Related Publication 20230061267A1 · Mar 2, 2023
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