Disaggregation of system-on-chip (SOC) architecture
Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
1. A multi-chip module comprising:
a plurality of semiconductor dies and a plurality of die-to-die interconnects, the plurality of semiconductor dies comprising:
a first semiconductor die including:
a plurality of graphics processing resources including a graphics multiprocessor, the graphics multiprocessor coupled with a first cache memory;
an interconnect fabric coupled with the first cache memory, wherein the first cache memory is associated with the graphics multiprocessor; and
a second cache memory coupled with the interconnect fabric, the interconnect fabric to couple the second cache memory with the first cache memory; and
a second semiconductor die coupled with the first semiconductor die in a 2.5-dimensional (2.5D) or 3-dimensional (3D) arrangement, the second semiconductor die including a third cache memory, wherein the third cache memory is accessible to the plurality of graphics processing resources of the first semiconductor die.
2. The multi-chip module as in claim 1 , wherein the second semiconductor die includes a memory controller coupled with the third cache memory.
3. The multi-chip module as in claim 2 , wherein the second semiconductor die includes a dynamic random-access memory (DRAM) device.
4. The multi-chip module as in claim 3 , wherein the DRAM device includes a plurality of stacks of high-bandwidth memory (HBM) devices.
5. The multi-chip module as in claim 1 , wherein the first semiconductor die and the second semiconductor die of the multi-chip module are distinct chiplets and the plurality of die-to-die interconnects include chiplet interconnects.
6. The multi-chip module as in claim 5 , wherein each of the first semiconductor die and the second semiconductor die couple with a package substrate via an interposer.
7. The multi-chip module as in claim 1 , the plurality of semiconductor dies including a third semiconductor die that includes external input/output interconnects for the multi-chip module.
8. The multi-chip module as in claim 7 , wherein the first semiconductor die is vertically stacked on the second semiconductor die.
9. The multi-chip module as in claim 8 , wherein the second semiconductor die couples with a package substrate via an interposer.
10. The multi-chip module as in claim 9 , wherein the interposer is an active interposer.
11. The multi-chip module as in claim 1 , wherein the first cache memory is a level 1 (L1) cache memory, the second cache memory is a level 2 (L2) cache memory, and the third cache memory is a level 3 (L3) cache memory.
12. The multi-chip module as in claim 1 , wherein the third cache memory is a first instance of the third cache memory and the plurality of semiconductor dies comprise a third semiconductor die including a second instance of the third cache memory.
13. The multi-chip module as in claim 1 , wherein the graphics multiprocessor has a single instruction multiple thread (SIMT) architecture.
14. An apparatus comprising:
a memory device; and
a multi-chip module coupled with the memory device, the multi-chip module comprising a plurality of semiconductor dies and a plurality of die-to-die interconnects, the plurality of semiconductor dies comprising a first semiconductor die, a second semiconductor die, and a third semiconductor die,
wherein the first semiconductor die, second semiconductor die, and third semiconductor die have a 2.5-dimensional (2.5D) or 3-dimensional (3D) arrangement,
wherein each of the first semiconductor die and the second semiconductor die comprise a plurality of graphics processing resources including a graphics multiprocessor, the graphics multiprocessor coupled with a first cache memory that is associated with the graphics multiprocessor, an interconnect fabric coupled with the first cache memory, and a second cache memory coupled with the interconnect fabric, the interconnect fabric to couple the second cache memory with the first cache memory, and
wherein the third semiconductor die couples with the first semiconductor die, the second semiconductor die and the third semiconductor die include a third cache memory, and the third cache memory is accessible to the plurality of graphics processing resources of the first semiconductor die and the second semiconductor die.
15. The apparatus as in claim 14 , wherein the third semiconductor die includes a memory controller coupled with the third cache memory.
16. The apparatus as in claim 15 , wherein the second semiconductor die includes a dynamic random-access memory (DRAM) device.
17. The apparatus as in claim 16 , wherein the DRAM device includes a plurality of stacks of high-bandwidth memory (HBM) devices.
18. The apparatus as in claim 14 , wherein the first semiconductor die, second semiconductor die, and third semiconductor die of the multi-chip module are distinct chiplets, the plurality of die-to-die interconnects include chiplet interconnects, and the multi-chip module includes a fourth semiconductor die that includes external input/output interconnects for the multi-chip module.
19. The apparatus as in claim 18 , wherein each of the first semiconductor die, second semiconductor die, and third semiconductor die couple with a package substrate via an interposer.
20. The apparatus as in claim 19 , wherein the interposer is an active interposer.
21. The apparatus as in claim 14 , wherein the first cache memory is a level 1 (L1) cache memory, the second cache memory is a level 2 (L2) cache memory, and the third cache memory is a level 3 (L3) cache memory.
22. The apparatus as in claim 14 , wherein the graphics multiprocessor has a single instruction multiple thread (SIMT) architecture.