IP Library › Granted Patent US 11,690,173
Granted Patent B2
US 11,690,173 · App. 17/674,837 · Granted Jun 27, 2023

Circuit board structure

Inventors: Tzyy-Jang Tseng (Taoyuan, TW); Chin-Sheng Wang (Taoyuan, TW); Ra-Min Tain (Hsinchu County, TW)
Assignee: Unimicron Technology Corp.
H05K1/0298H05K1/023H05K1/181H05K1/185H05K1/032H05K1/036H05K1/092H05K1/113H05K2201/0323
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Quick Facts
Patent No.
US 11,690,173
App. No.
17/674,837
Granted
Jun 27, 2023
Kind
B2
Abstract

A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, and at least one second build-up circuit layer. The dielectric substrate includes a through cavity penetrating the dielectric substrate. The embedded block is fixed in the through cavity. The embedded block includes a first through hole and a second through hole. The electronic component is disposed in the through hole of the embedded block. The first build-up circuit layer is disposed on the top surface of the dielectric substrate and covers the embedded block. The second build-up circuit layer is disposed on the bottom surface of the dielectric substrate and covers the embedded block.

Claims (10)

1. A circuit board structure, comprising: a dielectric substrate comprising a top surface and a bottom surface opposite to the top surface and comprising at least one through cavity penetrating the dielectric substrate; at least one embedded block fixed in the at least one through cavity, comprising a top surface and a bottom surface opposite to the top surface, and comprising at least one first through hole and at least one second through hole; at least one electronic component disposed in the at least one first through hole of the at least one embedded block; at least one first build-up circuit layer disposed on the top surface of the dielectric substrate and covering the at least one embedded block; at least one second build-up circuit layer disposed on the bottom surface of the dielectric substrate and covering the at least one embedded block; and at least one conductive through via disposed in the second through hole of the at least one embedded block, wherein the at least one conductive through via contacts and is directly electrically connected to the at least one first build-up circuit layer and the at least one second build-up circuit layer; wherein the at least one embedded block comprises conductive materials, the conductive materials comprise a metal, an alloy, or a metal mixed with a non-metallic material, and the non-metallic material comprises diamond or graphene.

2. The circuit board structure according to claim 1 , further comprising:

a connection layer disposed between the at least one first build-up circuit layer and the at least one second build-up circuit layer and electrically connected to the at least one first build-up circuit layer and the at least one second build-up circuit layer.

3. The circuit board structure according to claim 2 , wherein the connection layer is electrically connected to the at least one first build-up circuit layer and the at least one electronic component.

4. The circuit board structure according to claim 1 , wherein the at least one electronic component is a passive component.

5. The circuit board structure according to claim 1 , wherein the at least one electronic component is an active component.

6. The circuit board structure according to claim 5 , wherein the active component is a bare die or a packaged module.

7. The circuit board structure according to claim 1 , further comprising:

a dielectric material disposed in a gap between the at least one electronic component and the at least one embedded block and comprising a prepreg, a resin, or a gel.

8. The circuit board structure according to claim 7 , wherein the dielectric material is disposed in a gap between the at least one electronic component and the at least one second build-up circuit layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2022
From: TSENG, TZYY-JANG; WANG, CHIN-SHENG; TAIN, RA-MIN
To: UNIMICRON TECHNOLOGY CORP.
Reel/Frame 059083/0760 →
Priority Claims (1)
TW 110148855 · Dec 27, 2021 · national
Continuity (2)
Provisional Application 63213667 · Jun 22, 2021
Related Publication 20220408554A1 · Dec 22, 2022