Computational memory
A processing device includes a two-dimensional array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The device further includes interconnections among the two-dimensional array of processing elements to provide direct communication among neighboring processing elements of the two-dimensional array of processing elements. A processing element of the two-dimensional array of processing elements is connected to a first neighbor processing element that is immediately adjacent the processing element in a first dimension of the two-dimensional array. The processing element is further connected to a second neighbor processing element that is immediately adjacent the processing element in a second dimension of the two-dimensional array.
1. A non-transitory machine-readable medium comprising executable instructions to:
load a matrix of coefficients into an array of processing elements as serialized coefficients, the matrix of coefficients being a square submatrix of a non-square matrix;
load an input vector into the array of processing elements;
divide the non-square matrix into a plurality of submatrices including the square submatrix; and
perform a computation with the input vector and each of the plurality of submatrices by:
performing a parallel operation with the serialized coefficients in the array of processing elements and the input vector;
accumulating a result vector; and
rotating the result vector in the array of processing elements and repeating the performing of the parallel operation and the accumulating until the operation is complete; and
when the computation is complete, outputting the result vector.
2. The non-transitory machine-readable medium of claim 1 , wherein the instructions are further to:
combine each result vector of each performance of the computation for each respective submatrix of the plurality of submatrices to obtain a final result vector corresponding to the non-square matrix.