Semiconductor integrated circuit device and semiconductor system including the same
A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.
1. A semiconductor integrated circuit device comprising:
a power control signal generator configured to generate a power control signal when levels of first and second voltages are higher than set levels of the first and second voltages; and
a level shifter configured to receive the power control signal as a power voltage of the level shifter.
2. The semiconductor integrated circuit device according to claim 1 , wherein the power control signal generator includes:
a first detection circuit configured to detect the level of the first voltage and generate a first detection signal based on the detected level of the first voltage; and
a second detection circuit configured to detect the level of the second voltage and generate a second voltage detection signal based on the detected level of the second voltage, the first detection signal and a current control signal.
3. The semiconductor integrated circuit device according to claim 2 ,
wherein the first detection signal is enabled when the detected level of the first detection signal is higher than the set level of the first voltage, and
wherein the second detection circuit is configured to generate the second detection signal when the first detection signal is enabled.
4. The semiconductor integrated circuit device according to claim 2 , wherein the power control signal generator further includes:
a storage and output circuit configured to generate the power control signal and the current control signal based on the second detection signal.
5. The semiconductor integrated circuit device according to claim 2 ,
wherein the power control signal is generated by latching the second detection signal.
6. The semiconductor integrated circuit device according to claim 2 ,
wherein the current control signal is generated by delaying the second detection signal.
7. The semiconductor integrated circuit device according to claim 6 ,
wherein the second detection signal is disabled when the current control signal is enabled.
8. The semiconductor integrated circuit device according to claim 1 ,
wherein the power control signal generator includes at least one first type transistor, and the level shifter includes at least one second type transistor,
wherein the second type transistor and the first type transistor include internal voltages, respectively, and
wherein the internal voltages of the second type transistor are lower than the internal voltages of the first type transistor.
9. The semiconductor integrated circuit device according to claim 8 ,
wherein each of the first type transistor and the second type transistor includes a gate, a source and a drain, and
wherein the internal voltages of the first or second type transistor include a voltage between the gate and the drain, a voltage between the gate and the source and a voltage between the source and the drain.
10. The semiconductor integrated circuit device according to claim 8 ,
wherein the at least one second type transistor is a transistor for lowering the power voltage.
11. The semiconductor integrated circuit device according to claim 8 ,
wherein the first type transistor includes a gate insulating film with a first thickness, and the second type transistor includes a gate insulating film with a second thickness thinner than the first thickness.
12. The semiconductor integrated circuit device according to claim 1 , wherein the level shifter comprises:
a current mirror configured to receive an input signal in response to the first voltage and generate an output signal by mirroring a current corresponding to the second voltage based on a level of the input signal; and
an adjusting circuit coupled to a power voltage terminal which receives the second voltage in parallel to the current mirror and configured to adjust the voltage level of an output terminal of the current mirror.