Thermalization arrangement at cryogenic temperatures
An inventive embodiment comprises a thermalization arrangement at cryogenic temperatures. The arrangement comprises a dielectric substrate ( 2 ) layer on which substrate a device/s or component/s ( 1 ) are positionable. A heat sink component ( 4 ) is attached on another side of the substrate. The arrangement further comprises a conductive layer ( 5 ) between the substrate layer ( 2 ) and the heat sink component ( 4 ). A joint between the substrate layer ( 2 ) and the conductive layer ( 5 ) has minimal thermal boundary resistance. Another joint between the conductive layer ( 5 ) and the cooling heat sink layer ( 4 ) is electrically conductive.
1. A thermalization arrangement at cryogenic temperatures, wherein the arrangement comprises a dielectric substrate layer on which substrate a device/s or component/s are positionable, and a heat sink component attached on another side of the substrate, the arrangement further comprising a conductive layer between the substrate layer and the heat sink component, a joint between the substrate layer and the conductive layer having minimal phonon thermal boundary resistance, and in which energy of conductive layer phonons are arranged to be absorbed by electrons, and another joint between the conductive layer and the heat sink component being electrically conductive, wherein the conductive layer is degenerately doped silicon.
2. The thermalization arrangement according to claim 1 , wherein the substrate layer is a silicon based material.
3. The thermalization arrangement according to claim 1 , wherein the attachment between the heat sink component 4 and the conductive layer comprises an electrically conductive adhesive.
4. The thermalization arrangement according to claim 3 , wherein the attachment between the heat sink component and the conductive layer further comprises a metal layer between the conductive layer and the electrically conductive adhesive.
5. The thermalization arrangement according to claim 1 , wherein the heat sink component is a metal layer or a solid-state cooler.
6. The thermalization arrangement according to claim 1 , wherein the conductive layer comprises several galvanically isolated conductive areas.
7. The thermalization arrangement according to claim 6 , wherein a solid-state cooler is used to cool the conductive layer.
8. The thermalization arrangement according to claim 7 , wherein the solid-state cooler comprises of one or more daisy chains of two or more of solid-state coolers that each are electrically current biased in a way that an average voltage drop over each cooler provides optimal total cooling for the complete cooler assembly, the different coolers in the cooler chain are used to cool different galvanically isolated conductive areas of the conductive layer.
9. The thermalization arrangement according to claim 1 , wherein the substrate layer comprises a micrometer-scale conductor projection in the dielectric substrate forming galvanically isolated electron-phonon thermalization point below 5K to a node of said device or component.
10. The thermalization arrangement according to claim 9 , wherein the arrangement further comprises micrometer-scale conductor projections ( 8 B) in the dielectric substrate having altogether 2-10 micrometer-scale conductor projections, which form together said galvanically isolated thermalization point.
11. The thermalization arrangement according to claim 9 , wherein the micrometer-scale conductor projection has a width within range 1-100 μm.
12. The thermalization arrangement according to claim 9 , wherein the micrometer-scale conductor projection has a length, which has at least 5:1 ratio to the width of the micrometer-scale conductor projection.
13. The thermalization arrangement according to claim 9 , wherein the micrometer-scale conductor projection is a spike or a rod.
14. The thermalization arrangement according to claim 9 , wherein the micrometer-scale conductor projection is made of conducting material that is non-superconducting at a working temperature below 5 K.
15. The thermalization arrangement according to claim 1 , wherein multiple thermalisation elements are arranged in a series configuration in a way that an active cooling layer of the heat sink component is connecting to an element layer that has micro-meter-scale conductor projections, or connecting to a further conductive layer, the element layer or the further conductive layer being connected to another conductive layer, which in turn is connected to another active cooling layer.
16. The thermalization arrangement according to claim 15 , wherein the arrangement comprises a thin dielectric layer between the further conductive layer and the other conductive layer.