Contact resistance reduction in nanosheet device structure
Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.
1. A semiconductor device, comprising:
a nanosheet field-effect transistor device disposed on a semiconductor substrate, wherein the nano sheet field-effect transistor device comprises:
a plurality of nanosheet stack structures each comprising a plurality of semiconductor channel layers;
a gate structure on the nanosheet stack structures;
a gate sidewall spacer on the gate structure;
a source/drain region in contact with sidewalls of the nanosheet stack structures and on a portion of the gate sidewall spacer to define a trench between opposing sidewalls; and
a metal-based material disposed in the trench, on a top surface of the source/drain region and on the gate sidewall spacer;
wherein the source/drain region is disposed on the sidewalls of the nanosheet stack structures and on a portion of an oxide layer disposed over a portion of the semiconductor substrate;
wherein the source/drain region has a uniform thickness along the sidewalls of the nanosheet stack structures and on the portion of the gate sidewall spacer; and
wherein the trench extends through the source/drain region to the oxide layer.
2. The semiconductor device of claim 1 , wherein the trench extends to a depth in the source/drain region at least equal to a depth of the semiconductor channel layers in the nanosheet stack structures.
3. The semiconductor device of claim 1 , wherein the source/drain region is disposed on the sidewalls of the nanosheet stack structures and on a portion of the semiconductor substrate.
4. The semiconductor device of claim 1 , wherein a top surface of the metal-based material is coplanar with a top surface of the gate structure.
5. The semiconductor device of claim 1 , wherein the gate structure comprises a gate cap layer.
6. The semiconductor device of claim 1 , wherein the metal-based material comprises a trench silicide.
7. An integrated circuit, comprising:
one or more semiconductor devices, wherein at least one of the semiconductor devices comprises:
a nanosheet field-effect transistor device disposed on a semiconductor substrate, wherein the nano sheet field-effect transistor device comprises:
a plurality of nanosheet stack structures each comprising a plurality of semiconductor channel layers;
a gate structure on the nanosheet stack structures;
a gate sidewall spacer on the gate structure;
a source/drain region in contact with sidewalls of the nanosheet stack structures and on a portion of the gate sidewall spacer to define a trench between opposing sidewalls; and
a metal-based material disposed in the trench, on a top surface of the source/drain region and on the gate sidewall spacer;
wherein the source/drain region is disposed on the sidewalls of the nanosheet stack structures and on a portion of an oxide layer disposed over a portion of the semiconductor substrate;
wherein the source/drain region has a uniform thickness along the sidewalls of the nanosheet stack structures and on the portion of the gate sidewall spacer; and
wherein the trench extends through the source/drain region to the oxide layer.
8. The integrated circuit of claim 7 , wherein the trench extends to a depth in the source/drain region at least equal to a depth of the semiconductor channel layers in the nanosheet stack structures.
9. The integrated circuit of claim 7 , wherein the source/drain region is disposed on the sidewalls of the nanosheet stack structures and on a portion of the semiconductor substrate.
10. The integrated circuit of claim 7 , wherein a top surface of the metal-based material is coplanar with a top surface of the gate structure.
11. The integrated circuit of claim 7 , wherein the gate structure comprises a gate cap layer.
12. The integrated circuit of claim 7 , wherein the metal-based material comprises a trench silicide.
13. A semiconductor device, comprising:
a nanosheet field-effect transistor device disposed on a semiconductor substrate, wherein the nanosheet field-effect transistor device comprises:
a nanosheet stack structure comprising a semiconductor channel layer;
a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure; and
a metal-based source/drain contact material disposed in a trench in the source/drain region;
wherein the source/drain region has a uniform thickness along the end portion of the semiconductor channel layer of the nanosheet stack structure;
wherein the source/drain region is disposed on the end portion of the semiconductor channel layer and on a portion of an oxide layer disposed over a portion of the semiconductor substrate; and
wherein the trench extends through the source/drain region to the oxide layer.
14. The semiconductor device of claim 13 , further comprising a gate structure on the nanosheet stack structure.
15. The semiconductor device of claim 14 , wherein the gate structure comprises a gate sidewall spacer, and the source/drain region is in contact with at least a portion of the gate sidewall spacer.
16. The semiconductor device of claim 15 , wherein the metal-based source/drain contact material is disposed in the trench and on the gate sidewall spacer.
17. The semiconductor device of claim 14 , wherein the gate structure comprises a gate cap layer.
18. The semiconductor device of claim 13 , wherein the trench extends to a depth in the source/drain region at least equal to a depth of the semiconductor channel layer in the nanosheet stack structure.
19. The semiconductor device of claim 14 , wherein a top surface of the metal-based source/drain contact material is coplanar with a top surface of the gate structure.
20. The semiconductor device of claim 13 , wherein the metal-based source/drain contact material comprises a trench silicide.