Method and apparatus to select a plane in a NAND flash die to store a read-only reserved block
Manufacturing yield loss of NAND Flash dies is reduced by selecting a plane to store a read-only reserved block and another plane to store a backup read-only reserved block based on the Number of Valid Blocks (NVB) blocks in each plane in the NAND Flash array.
1 . A non-volatile memory device, comprising:
a NAND flash array comprising a plurality of planes, a read-only reserved block in one of the plurality of planes to store NAND flash die specific information, wherein the read-only reserved block is stored in a first plane that is selected among the plurality of planes based on the first plane having the highest number of valid blocks; and
control circuitry comprising a plurality of fuses, the control circuitry to obtain a location of the read-only reserved block encoded in the plurality of fuses during initialization of the non- volatile memory device after power-on reset;
wherein the NAND flash die specific information is also stored in a backup read-only reserved block in a second plane, and the second plane is selected among the plurality of planes to store the backup read-only reserved block based on the second plane having the second highest number of valid blocks.
2 . The non-volatile memory device of claim 1 , wherein the plurality of fuses include four fuses, and the plurality of planes include four planes.
3 . The non-volatile memory device of claim 1 , wherein the NAND flash array is a three-dimensional (3D) NAND flash array.
4 . The non-volatile memory device of claim 1 , wherein the plurality of planes include an even number of planes, and the even number is greater than two.
5 . A system, comprising:
a memory controller; and
a non-volatile memory device coupled with the memory controller, the non-volatile memory device comprising:
a NAND flash array comprising a plurality of planes, a read-only reserved block in one of the plurality of planes to store NAND flash die specific information, wherein the read-only reserved block is stored in a first plane that is selected among the plurality of planes based on the first plane having the highest number of valid blocks; and
control circuitry comprising a plurality of fuses, the control circuitry to obtain a location of the read-only reserved block encoded in the plurality of fuses during initialization of the non-volatile memory device after power-on reset;
wherein the NAND flash die specific information is also stored in a backup read-only reserved block in a second plane, and the second plane is selected among the plurality of planes to store the backup read-only reserved block based on the second plane having the second highest number of valid blocks.
6 . The system of claim 5 , further comprising on or more of:
a display communicatively coupled to at least one processor; or
a power supply to provide power to the system.
7 . The system of claim 5 , wherein the plurality of fuses include four fuses, and the plurality of planes include four planes.
8 . The system of claim 5 , wherein the NAND flash array is a three-dimensional (3D) NAND flash array.
9 . The system of claim 5 , wherein the plurality of planes include an even number of planes, and the even number is greater than two.
10 . A method, comprising:
obtaining a location of a read-only reserved block encoded in a plurality of fuses in control circuitry of a non-volatile memory device during initialization of the non-volatile memory device after power-on reset, the non-volatile memory device comprising a NAND flash array comprising plurality of planes, wherein the read-only reserved block is stored in a first plane that is selected among the plurality of planes based on the first plane having the highest number of valid blocks; and
reading NAND flash die specific information in the read-only reserved block;
wherein the NAND flash die specific information is also stored in a backup read-only reserved block in a second plane, and the second plane is selected among the plurality of planes to store the backup read-only reserved block based on the second plane having the second highest number of valid blocks.
11 . The method of claim 10 , wherein the plurality of fuses include four fuses, and the plurality of planes include four planes.
12 . The method of claim 10 , wherein the NAND flash array is a three-dimensional (3D) NAND flash array.
13 . The method of claim 10 , wherein the plurality of planes include an even number of planes, and the even number is greater than two.
14 . The non-volatile memory device of claim 1 , wherein the NAND flash die specific information includes one or more of: a memory cell related voltage, timing parameters, column repairs, block repairs, and bad block address information.
15 . The system of claim 5 , wherein the NAND flash die specific information includes one or more of: a memory cell related voltage, timing parameters, column repairs, block repairs, and bad block address information.
16 . The method of claim 10 , wherein the NAND flash die specific information includes one or more of: a memory cell related voltage, timing parameters, column repairs, block repairs, and bad block address information.
17 . The non-volatile memory device of claim 1 , wherein each of the plurality of planes has one or more respective registers that are configured to facilitate a plurality of concurrent memory operations on the plurality of planes.
18 . The method of claim 10 , wherein the second plane is distinct from the first plane.
19 . The system of claim 5 , wherein the ready-only reserved block is excluded from the highest number of valid blocks of the first plane, and the block ready-only reserved block is excluded from the second highest number of valid blocks of the second plane.
20 . The non-volatile memory device of claim 1 , wherein the control circuitry is configured to load the NAND flash die specific information from the read-only reserved block or the backup read-only reserved block during initialization of the non-volatile memory device.