IP Library › Granted Patent US 12,504,912
Granted Patent B2
US 12,504,912 · App. 17/678,865 · Granted Dec 23, 2025

Soft read for NVM that is subject to destructive reads

Inventors: Zion Kwok (Burnaby, CA); Santhosh Vanaparthy (Santa Clara, CA); Ravi Motwani (Fremont, CA); Poovaiah Manavattira Palangappa (San Jose, CA)
Assignee: Intel Corporation
G06F3/0655G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 12,504,912
App. No.
17/678,865
Granted
Dec 23, 2025
Kind
B2
Abstract

Techniques and mechanisms for supporting error correction of data accessed in a non-volatile (NVM) memory. In an embodiment, a memory controller performs reads each of the same codeword from the NVM, wherein a first read is based on a first reference voltage, and a second read is based on a second reference voltage. Based on the first read and the second read, confidence values are assigned each to respective bits of the codeword. Error correction comprises applying a weights to respective bits of the codeword based on the confidence values. In other embodiments, a relatively low confidence value is assigned to codeword bits that have a different value for the first read and the second read.

Claims (43)

1 . An electronic apparatus, comprising:

one or more substrates; and

a controller coupled to the one or more substrates, the controller including circuitry to:

control access to a nonvolatile memory with a destructive read characteristic and memory cells programmed to a high resistance state that corresponds to a first threshold voltage and a low resistance state that correspond to a second threshold voltage;

perform a first read of a codeword from the nonvolatile memory at a first reference voltage of a low confidence zone, wherein the low confidence zone is between the first and second threshold voltages;

perform a second read of the codeword from the nonvolatile memory at a second reference voltage of the low confidence zone, wherein the second threshold voltage is lower than the first reference voltage;

assign a first confidence value to first bits of the codeword based on a determination that the first bits have a different value for the first read of the codeword and the second read of the codeword, wherein the first confidence value is to be lower than a second confidence value which is to be assigned to second bits of the codeword that have a same value for the first read of the codeword and the second read of the codeword; and

apply weights in an error code correction decoder based on the first confidence value and the second confidence value, wherein the circuitry is to apply a first weight to bits of the codeword that correspond to the first reference voltage, and wherein the first weight is greater than a second weight which is to be applied to bits of the codeword that correspond to the second reference voltage.

2 . The electronic apparatus of claim 1 , wherein the circuitry is further to:

correct an error in the codeword based on the first confidence value and the second confidence value.

3 . The electronic apparatus of claim 1 , wherein the circuitry is further to:

determine respective levels of the first reference voltage and the second reference voltage.

4 . The electronic apparatus of claim 3 , wherein the circuitry is further to:

assign a log-likelihood ratio (LLR) value to one or more bits of the codeword based on one of the first confidence value or the second confidence value.

5 . The electronic apparatus of claim 4 , wherein the circuitry is to:

assign a LLR value of zero to the first bits.

6 . An electronic system, comprising:

nonvolatile memory with a destructive read characteristic and memory cells programmed to a high resistance state that corresponds to a first threshold voltage and a low resistance state that correspond to a second threshold voltage; and

a controller communicatively coupled to the nonvolatile memory, the controller including circuitry to:

perform a first read of a codeword from the nonvolatile memory at a first reference voltage of a low confidence zone, wherein the low confidence zone is between the first and second threshold voltages;

perform a second read of the codeword from the nonvolatile memory at a second reference voltage of the low confidence zone, wherein the second threshold voltage is lower than the first reference voltage;

assign a first confidence value to first bits of the codeword based on a determination that the first bits have a different value for the first read of the codeword and the second read of the codeword, wherein the first confidence value is to be lower than a second confidence value which is to be assigned to second bits of the codeword that have a same value for the first read of the codeword and the second read of the codeword; and

apply weights in an error code correction decoder based on the first confidence value and the second confidence value, wherein the circuitry is to apply a first weight to bits of the codeword that correspond to the first reference voltage, and wherein the first weight is greater than a second weight which is to be applied to bits of the codeword that correspond to the second reference voltage.

7 . The electronic system of claim 6 , wherein the circuitry is further to:

correct an error in the codeword based on the first confidence value and the second confidence value.

8 . The electronic system of claim 6 , wherein the circuitry is further to:

determine respective levels of the first reference voltage and the second reference voltage.

9 . The electronic system of claim 8 , wherein the circuitry is further to:

assign a log-likelihood ratio (LLR) value to one or more bits of the codeword based on one of the first confidence value or the second confidence value.

10 . The electronic system of claim 9 , wherein the circuitry is further to:

assign a LLR value of zero to the first bits.

11 . A method, comprising:

controlling access to a nonvolatile memory with a destructive read characteristic and memory cells programmed to a high resistance state that corresponds to a first threshold voltage and a low resistance state that correspond to a second threshold voltage;

performing a first read of a codeword from the nonvolatile memory at a first reference voltage of a low confidence zone, wherein the low confidence zone is between the first and second threshold voltages;

performing a second read of the codeword from the nonvolatile memory at a second reference voltage of the low confidence zone, wherein the second threshold voltage is lower than the first reference voltage;

assigning a first confidence value to first bits of the codeword based on a determination that the first bits have a different value for the first read of the codeword and the second read of the codeword, wherein the first confidence value is lower than a second confidence value assigned to second bits of the codeword that have a same value for the first read of the codeword and the second read of the codeword; and

applying weights in an error code correction decoder based on the first confidence value and the second confidence value, comprising applying a first weight to bits of the codeword that correspond to the first reference voltage, and wherein the first weight is greater than a second weight which is to be applied to bits of the codeword that correspond to the second reference voltage.

12 . The method of claim 11 , further comprising:

correcting an error in the codeword based on the first confidence value and the second confidence value.

13 . The method of claim 11 , further comprising:

determining respective levels of the first reference voltage and the second reference voltage.

14 . The method of claim 13 , further comprising:

assigning a log-likelihood ratio (LLR) value to one or more bits of the codeword based on one of the first confidence value or the second confidence value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2022
From: KWOK, ZION; VANAPARTHY, SANTHOSH; MOTWANI, RAVI; PALANGAPPA, POOVAIAH MANAVATTIRA
To: INTEL CORPORATION
Reel/Frame 059082/0354 →
Continuity (1)
Related Publication 20220179582A1 · Jun 9, 2022
References Cited (5)
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US 20150095736A1 · Leem et al. · 2015 [cited by applicant]
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